diff --git a/HDL/common/skywater_function_verification.v b/HDL/common/skywater_function_verification.v
new file mode 100644
index 0000000..cb4312c
--- /dev/null
+++ b/HDL/common/skywater_function_verification.v
@@ -0,0 +1,13 @@
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Thu Nov  5 10:40:44 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+`define UNIT_DELAY #0.01
+
+`define FUNCTIONAL 1