mirror of https://github.com/lnis-uofu/SOFA.git
[Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist
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@ -103,7 +103,8 @@
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<!-- Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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@ -288,7 +289,7 @@
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
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<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
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<global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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