diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml index e6d1b24..be0309b 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml @@ -186,7 +186,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml index 9880c7a..bce7666 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml @@ -186,7 +186,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml index a5efd99..915e1b7 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml @@ -186,7 +186,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml index 1ebbe06..c7485a1 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml @@ -186,7 +186,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml index 1bbf6d7..57ca9fa 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml @@ -186,7 +186,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml index a47ab93..1f341b1 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml @@ -185,7 +185,7 @@ - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 0000000..d4ee0fa --- /dev/null +++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml index 186a4d1..ee61144 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml @@ -187,14 +187,14 @@ - + - + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml index 6242733..c372a49 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml @@ -188,11 +188,11 @@ - - + + - - + + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 0000000..8885db5 --- /dev/null +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,665 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.regin clb.scin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.regout clb.scout + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/HDL/common/digital_io_hd.v b/HDL/common/digital_io_hd.v index 5267d22..b1431a3 100644 --- a/HDL/common/digital_io_hd.v +++ b/HDL/common/digital_io_hd.v @@ -42,3 +42,22 @@ module GPOUT ( .A (A), .X (Y) ); endmodule + +//----------------------------------------------------- +// Function : A minimum embedded I/O +// just an overlay to interface other components +//----------------------------------------------------- +module EMBEDDED_IO ( + input SOC_IN, // Input to drive the inpad signal + output SOC_OUT, // Output the outpad signal + output SOC_DIR, // Output the directionality + output FPGA_IN, // Input data to FPGA + input FPGA_OUT, // Output data from FPGA + input FPGA_DIR // direction control +); + + assign FPGA_IN = SOC_IN; + assign SOC_OUT = FPGA_OUT; + assign SOC_DIR = FPGA_DIR; +endmodule + diff --git a/HDL/common/skywater_function_verification.v b/HDL/common/skywater_function_verification.v new file mode 100644 index 0000000..cb4312c --- /dev/null +++ b/HDL/common/skywater_function_verification.v @@ -0,0 +1,13 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +// Date: Thu Nov 5 10:40:44 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define UNIT_DELAY #0.01 + +`define FUNCTIONAL 1 diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf new file mode 100644 index 0000000..2d690ad --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf new file mode 100644 index 0000000..86a19dd --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf new file mode 100644 index 0000000..58349ae --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test=