From e63cb7ca89ffc45012c15a5b02b44a698c503040 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 10:23:30 -0700 Subject: [PATCH] [Testbench] Rename testbench top module to be compatible with verification scripts --- .../postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v | 4 ++-- .../postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v index fb366da..8505896 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ed96f64d008f69b13c352cefea841509291d29edf65fdad1f8d5ae5f2a972499 -size 29471 +oid sha256:4536eee5498c65f120e49e23ad8f5659ecfdefe6693c673920255cb087b3bd5b +size 29488 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v index fa2dc67..b2c7c8c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aa307fe506d4107e78867547f28e9533691c57b6ccea22f24afb389b7d61ce5a -size 29307 +oid sha256:3d8fd9493ad2339e27c6723fb601dde18b0c3698534b6241dd05de0af6c1d7aa +size 29324