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Merge pull request #134 from lnis-uofu/roman_dev 

Fix typos causing the unknown `write_verilog_testbench` command errors
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Grant Brown 2022-02-04 16:21:28 -07:00 committed by GitHub
parent 47b839fa0a bc43b6b9b3
commit e508bdd905
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 3 additions and 3 deletions
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2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -54,7 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge

2
FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga
View File

@ -45,7 +45,7 @@ write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping