diff --git a/SOFA_A/CommonFiles/generate_clock_connectivity.py b/SOFA_A/CommonFiles/generate_clock_connectivity.py index 031725f..24bdee9 100644 --- a/SOFA_A/CommonFiles/generate_clock_connectivity.py +++ b/SOFA_A/CommonFiles/generate_clock_connectivity.py @@ -41,22 +41,24 @@ PICKLE_DIR = f"{RELEASE_DIR}/pickle" def main(): + """ + Main method to create clock tree + """ + fpga_width = FPGA_SIZE_X+1 + fpga_height = FPGA_SIZE_Y+1 - fpga_width = FPGA_SIZE_X - fpga_height = FPGA_SIZE_Y - - WIDTH = fpga_width*2+1 - HEIGHT = fpga_height*2+1 + WIDTH = fpga_width + 1 + HEIGHT = fpga_height + 1 p_manager = ConnectionPattern(WIDTH, HEIGHT) l2_patt = p_manager.connections - l2_patt.cursor = (int(WIDTH / 2) + 1, 0) - l2_patt.move_y(steps=int(WIDTH / 2) + 1) + l2_patt.cursor = (int(WIDTH) + 1, 0) + l2_patt.move_y(steps=int(WIDTH) + 1) l2_patt.merge(p_manager.get_htree(WIDTH)) l2_patt.set_color("red") - for x in range(2): - for y in range(2): - l2_patt.push_connection_down((5 + (x * 8), 5 + (y * 8))) + # for x in range(2): + # for y in range(2): + # l2_patt.push_connection_down((5 + (x * 8), 5 + (y * 8))) svg = p_manager.render_pattern(title=PROJ_NAME, scale=7) @@ -65,6 +67,7 @@ def main(): save_svg_with_background(svg, f"{SVG_DIR}/{PROJ_NAME}_clock0_leve2_tree.svg") + return # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # level1 connection pattern # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = diff --git a/SOFA_A/CommonFiles/render_sofa_a.py b/SOFA_A/CommonFiles/render_sofa_a.py index 560cd69..93afbbf 100644 --- a/SOFA_A/CommonFiles/render_sofa_a.py +++ b/SOFA_A/CommonFiles/render_sofa_a.py @@ -70,22 +70,18 @@ def main(): w = fpga.get_width() h = fpga.get_height() - for y in range(2, h): + for y in range(1, h): x = 0 - instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_", - f"cbx_{x+1}__{y}_", f"clb_{x+1}__{y}_", - f"cby_{x+1}__{y}_", f"sb_{x+1}__{y}_"] + instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_"] fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") x = w instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_", f"cbx_{x}__{y}_", f"clb_{x}__{y}_"] fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") - for x in range(2, w): + for x in range(1, w): y = 0 - instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_", - f"cby_{x}__{y+1}_", f"clb_{x}__{y+1}_", - f"cbx_{x}__{y+1}_", f"sb_{x}__{y+1}_"] + instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_"] fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") y = h instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_", @@ -93,8 +89,8 @@ def main(): fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}") # Main tile - for x in range(2, w): - for y in range(2, h): + for x in range(1, w): + for y in range(1, h): fpga.merge_symbol( [ f"clb_{x}__{y}_", f"sb_{x}__{y}_", f"cbx_{x}__{y}_", f"cby_{x}__{y}_"], @@ -102,8 +98,7 @@ def main(): # Corner Tiles fpga.merge_symbol( - [f"cby_0__{h}_", f"sb_0__{h}_", f"cbx_1__{h}_", - f"cby_1__{h}_", f"sb_1__{h}_"], "corner_merged_ltop") + [f"cby_0__{h}_", f"sb_0__{h}_"], "corner_merged_ltop") fpga.merge_symbol( [f"cbx_{w}__{h}_", f"cby_{w}__{h}_", f"clb_{w}__{h}_", f"sb_{w}__{h}_"], "corner_merged_rtop") @@ -111,11 +106,7 @@ def main(): [f"cbx_{w}__0_", f"cbx_{w}__1_", f"sb_{w}__0_", f"sb_{w}__1_", f"cby_{w}__1_", f"clb_{w}__1_"], "corner_merged_rbottom") - fpga.merge_symbol( - ["cbx_1__0_", "cbx_1__1_", - "sb_0__0_", "sb_0__1_", - "sb_1__0_", "sb_1__1_", - "cby_1__1_", "clb_1__1_"], "corner_merged_lbottom") + fpga.merge_symbol(["sb_0__0_",], "corner_merged_lbottom") # ====================== END ========================= diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log index 335c558..2218da2 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log @@ -268,11 +268,11 @@ Logic Element (fle) detailed count: LEs used for logic only : 1 LEs used for registers only : 0 -Incr Slack updates 1 in 2.224e-06 sec -Full Max Req/Worst Slack updates 1 in 2.152e-06 sec +Incr Slack updates 1 in 2.269e-06 sec +Full Max Req/Worst Slack updates 1 in 1.885e-06 sec Incr Max Req/Worst Slack updates 0 in 0 sec Incr Criticality updates 0 in 0 sec -Full Criticality updates 1 in 1.857e-06 sec +Full Criticality updates 1 in 1.959e-06 sec Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. Warning 28: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. Warning 29: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. @@ -507,11 +507,11 @@ Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wireleng (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- 1 0.0 0.0 0 226 3 3 0 ( 0.000%) 27 ( 0.3%) 13.980 -13.98 -13.980 0.000 0.000 N/A -Incr Slack updates 4 in 1.9664e-05 sec -Full Max Req/Worst Slack updates 1 in 2.711e-06 sec -Incr Max Req/Worst Slack updates 3 in 1.4906e-05 sec -Incr Criticality updates 3 in 1.5953e-05 sec -Full Criticality updates 1 in 2.375e-06 sec +Incr Slack updates 4 in 1.9618e-05 sec +Full Max Req/Worst Slack updates 1 in 5.491e-06 sec +Incr Max Req/Worst Slack updates 3 in 1.0638e-05 sec +Incr Criticality updates 3 in 1.0959e-05 sec +Full Criticality updates 1 in 5.516e-06 sec Restoring best routing Critical path: 13.98 ns Successfully routed after 1 routing iterations. @@ -658,11 +658,11 @@ Final setup slack histogram: Final geomean non-virtual intra-domain period: nan ns (nan MHz) Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz) -Incr Slack updates 1 in 7.13e-06 sec -Full Max Req/Worst Slack updates 1 in 5.927e-06 sec +Incr Slack updates 1 in 4.1293e-05 sec +Full Max Req/Worst Slack updates 1 in 4.863e-06 sec Incr Max Req/Worst Slack updates 0 in 0 sec Incr Criticality updates 0 in 0 sec -Full Criticality updates 1 in 5.366e-06 sec +Full Criticality updates 1 in 4.307e-06 sec --line removed-- VPR suceeded --line removed-- @@ -992,11 +992,11 @@ Building annotation for post-routing and clustering synchornization results...Do Building annotation for mapped blocks on grid locations...Done User specified the operating clock frequency to use VPR results Use VPR critical path delay 1.6776e-17 [ns] with a 20 [%] slack in OpenFPGA. -Incr Slack updates 1 in 5.809e-06 sec -Full Max Req/Worst Slack updates 1 in 3.941e-06 sec +Incr Slack updates 1 in 1.3184e-05 sec +Full Max Req/Worst Slack updates 1 in 4.953e-06 sec Incr Max Req/Worst Slack updates 0 in 0 sec Incr Criticality updates 0 in 0 sec -Full Criticality updates 1 in 3.894e-06 sec +Full Criticality updates 1 in 4.313e-06 sec Will apply operating clock frequency 59.609 [MHz] to simulations User specified the number of operating clock cycles to be inferred from signal activities Average net density: 0.42 @@ -1314,9 +1314,9 @@ Finish execution with 0 errors --line removed-- Thank you for using OpenFPGA! -Incr Slack updates 2 in 1.3494e-05 sec -Full Max Req/Worst Slack updates 1 in 5.371e-06 sec -Incr Max Req/Worst Slack updates 1 in 6.386e-06 sec +Incr Slack updates 2 in 1.3959e-05 sec +Full Max Req/Worst Slack updates 1 in 5.036e-06 sec +Incr Max Req/Worst Slack updates 1 in 6.307e-06 sec Incr Criticality updates 0 in 0 sec -Full Criticality updates 2 in 1.2969e-05 sec +Full Criticality updates 2 in 2.5362e-05 sec 0 \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg index 60fb642..120fc3a 100644 --- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg @@ -83,78 +83,114 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + + + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -173,6 +209,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -191,6 +230,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -209,6 +251,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -227,6 +272,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -245,6 +293,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -263,8 +314,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + + @@ -272,8 +323,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + + @@ -571,6 +622,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + @@ -583,6 +636,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + @@ -595,36 +650,49 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + + + + + + + + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg index 4f3f389..e2a3c44 100644 --- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg @@ -1,5 +1,5 @@ - + @@ -35,79 +35,55 @@ ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - FPGA88_SOFA_A + FPGA88_SOFA_A diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg index 3ee53cd..1a2d04d 100644 --- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg @@ -83,78 +83,114 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + + + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -173,6 +209,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -191,6 +230,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -209,6 +251,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -227,6 +272,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -245,6 +293,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} + + + @@ -263,8 +314,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + + @@ -272,8 +323,8 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - + +