From e17d51aa9f759ac78db3dc1a1cae1b18a0bfab29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 17:49:16 -0700 Subject: [PATCH] [Testbench] Bug fix in using power pins --- .../verilog_testbench/scff_test_post_pnr_include_netlists.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 72bdd92..930469b 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -33,9 +33,9 @@ // ------ Include fabric top-level netlists ----- `ifndef USE_POWER_PINS - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" -`else `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" `endif `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v"