From dff324a1f316e69a88dcf045b4c8edd69eadbe00 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Fri, 4 Jun 2021 16:55:36 -0600 Subject: [PATCH] ff conversion --- .../generate_testbench/config/task.conf | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task.conf diff --git a/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task.conf new file mode 100644 index 0000000..578929c --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_130nm/130nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga +openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml +openfpga_vpr_device_layout=auto +openfpga_vpr_route_chan_width=40 # Don't care +openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr +openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v +external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml # Don't care +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v + +[ARCHITECTURES] +arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=/home/apond/sofa/BENCHMARK/vexriscv/vexriscv_small.v + +[SYNTHESIS_PARAM] +bench0_top = VexRiscv + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +# none