diff --git a/SOFA_A/CommonFiles/generate_clock_connectivity.py b/SOFA_A/CommonFiles/generate_clock_connectivity.py new file mode 100644 index 0000000..031725f --- /dev/null +++ b/SOFA_A/CommonFiles/generate_clock_connectivity.py @@ -0,0 +1,153 @@ +""" +This cript genertes the clock tree for the FPGA +""" + +import logging +import os +import pickle +from copy import deepcopy +from glob import glob +from os import environ +from os.path import basename, dirname, realpath +import matplotlib.pyplot as plt +import networkx as nx +from networkx.drawing.nx_pydot import to_pydot + +import spydrnet as sdn + +from spydrnet_physical.util import ConnectionPattern, ConnectPointList, ConnectPoint +from svgwrite.container import Group, Style +from spydrnet_physical.util import FPGAGridGen +from copy import deepcopy + + +logger = logging.getLogger("spydrnet_logs") + +PROJ_NAME = basename(dirname(realpath(__file__))) +LAYOUT = environ.get("LAYOUT", "ultimate") + +EXTRA_STYLE = """ +text{display:none;} +.marker{display:none;} +""" + +PROJ_NAME = os.environ["PROJ_NAME"] +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +FPGA_SIZE_X = int(os.environ["FPGA_SIZE_X"]) +FPGA_SIZE_Y = int(os.environ["FPGA_SIZE_Y"]) +LAYOUT = os.environ["LAYOUT"] +SVG_DIR = f"{RELEASE_DIR}/svg" +PICKLE_DIR = f"{RELEASE_DIR}/pickle" + + +def main(): + + fpga_width = FPGA_SIZE_X + fpga_height = FPGA_SIZE_Y + + WIDTH = fpga_width*2+1 + HEIGHT = fpga_height*2+1 + + p_manager = ConnectionPattern(WIDTH, HEIGHT) + l2_patt = p_manager.connections + l2_patt.cursor = (int(WIDTH / 2) + 1, 0) + l2_patt.move_y(steps=int(WIDTH / 2) + 1) + l2_patt.merge(p_manager.get_htree(WIDTH)) + l2_patt.set_color("red") + for x in range(2): + for y in range(2): + l2_patt.push_connection_down((5 + (x * 8), 5 + (y * 8))) + + svg = p_manager.render_pattern(title=PROJ_NAME, scale=7) + + svg.saveas(f"{SVG_DIR}/{PROJ_NAME}_clock0_leve2_clear_tree.svg", + pretty=True, indent=4) + save_svg_with_background(svg, + f"{SVG_DIR}/{PROJ_NAME}_clock0_leve2_tree.svg") + + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # level1 connection pattern + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + p_manager = ConnectionPattern(WIDTH, HEIGHT) + l1_patt = p_manager.connections + for x in range(2): + for y in range(2): + xx, yy = 1 + (x * 8), 1 + (y * 8) + l1_patt.merge(p_manager.get_htree(8).translate(xx, yy)) + l1_patt.push_connection_down((xx+2, yy+2)) + l1_patt.push_connection_down((xx+2, yy+6)) + l1_patt.push_connection_down((xx+6, yy+2)) + l1_patt.push_connection_down((xx+6, yy+6)) + l1_patt.set_color("blue") + svg = p_manager.render_pattern(title="L1 Pattern", scale=7) + save_svg_with_background( + svg, f"{SVG_DIR}/{PROJ_NAME}_clock0_leve1_tree.svg") + + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # level2 connection pattern + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + p_manager = ConnectionPattern(WIDTH, HEIGHT) + l0_patt = p_manager.connections + + for x in range(2): + for y in range(2): + xx, yy = 5 + (x * 8), 5 + (y * 8) + l0_patt.merge(p_manager.get_htree(4).translate(xx-4, yy-4)) + l0_patt.merge(p_manager.get_htree(4).translate(xx, yy-4)) + l0_patt.merge(p_manager.get_htree(4).translate(xx, yy)) + l0_patt.merge(p_manager.get_htree(4).translate(xx-4, yy)) + + for x in range(4): + for y in range(4): + ydir = -1 if y % 2 else 1 + pt = ConnectPoint(3 + (x * 4), 3 + (y * 4) + + ydir, 3 + (x * 4), 3 + (y * 4)) + l0_patt.add_connect_point(pt) + l0_patt.pull_connection_up(pt) + l0_patt.set_color("grey") + svg = p_manager.render_pattern(title="L0 Pattern", scale=7) + save_svg_with_background( + svg, f"{SVG_DIR}/{PROJ_NAME}_clock0_leve0_tree.svg") + + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Combined all patterns + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + p_manager = ConnectionPattern(WIDTH, HEIGHT) + combine_pattern = p_manager.connections + combine_pattern.merge(l0_patt) + combine_pattern.merge(l1_patt) + combine_pattern.merge(l2_patt) + svg = p_manager.render_pattern(title="Combined Pattern", scale=7) + save_svg_with_background( + svg, f"{SVG_DIR}/{PROJ_NAME}_clock0_combined_tree.svg") + +def save_svg_with_background(svg, filename, add_marker=False): + ''' + Save SVG floorplan file + ''' + fpga = pickle.load( + open(f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "rb")) + + scalex, scaley = 1, 1 + + # Add main group + groups = {ele["id"]: ele for ele in svg.elements if isinstance(ele, Group)} + main_group = groups["main"] + + for style in [ele for ele in svg.elements if isinstance(ele, Style)]: + fpga.dwg.defs.add(style) + fpga.dwg.defs.add(fpga.dwg.style(EXTRA_STYLE)) + + connections_dwg = fpga.dwg.add( + Group(id="connection", + transform=f"scale({scalex},-{scaley}) translate(-2, -2)") + ) + + for ele in main_group.elements: + connections_dwg.add(ele) + fpga.dwg.saveas(filename, pretty=True, indent=4) + logger.info("Saving clock rendering in %s", filename) + + +if __name__ == "__main__": + main() diff --git a/SOFA_A/FPGA88_SOFA_A/config.sh b/SOFA_A/FPGA88_SOFA_A/config.sh index 1b17572..b1afd87 100644 --- a/SOFA_A/FPGA88_SOFA_A/config.sh +++ b/SOFA_A/FPGA88_SOFA_A/config.sh @@ -18,6 +18,7 @@ export_ NETLIST_SYNTH_SCRIPT = "../CommonFiles/sofa_netlist_synth_script.sh" export_ RESTRUCT_NETLIST = "../CommonFiles/restructure_fabric_sofa_a.py" export_ CUSTOM_MODULES_LIST = "./${TASK_DIR_NAME}/CustomModules/custom_module.txt" export_ GLOBAL_FT_SCRIPT = "../CommonFiles/generate_global_signals_connectivity.py" +export_ CLOCK_FT_SCRIPT = "../CommonFiles/generate_clock_connectivity.py" # Complete Chip (fpga_top) or eFPGA (fpga_core) export_ DESIGN_NAME = fpga_core diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_combined_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_combined_tree.svg new file mode 100644 index 0000000..b89ed4f --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_combined_tree.svg @@ -0,0 +1,1130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sb_0__0_ + cby_0__1_ + sb_0__1_ + cby_0__2_ + sb_0__2_ + cby_0__3_ + sb_0__3_ + cby_0__4_ + sb_0__4_ + cby_0__5_ + sb_0__5_ + cby_0__6_ + sb_0__6_ + cby_0__7_ + sb_0__7_ + cby_0__8_ + sb_0__8_ + cbx_1__0_ + clb_1__1_ + cbx_1__1_ + clb_1__2_ + cbx_1__2_ + clb_1__3_ + cbx_1__3_ + clb_1__4_ + cbx_1__4_ + clb_1__5_ + cbx_1__5_ + clb_1__6_ + cbx_1__6_ + clb_1__7_ + cbx_1__7_ + clb_1__8_ + cbx_1__8_ + sb_1__0_ + cby_1__1_ + sb_1__1_ + cby_1__2_ + sb_1__2_ + cby_1__3_ + sb_1__3_ + cby_1__4_ + sb_1__4_ + cby_1__5_ + sb_1__5_ + cby_1__6_ + sb_1__6_ + cby_1__7_ + sb_1__7_ + cby_1__8_ + sb_1__8_ + cbx_2__0_ + clb_2__1_ + cbx_2__1_ + clb_2__2_ + cbx_2__2_ + clb_2__3_ + cbx_2__3_ + clb_2__4_ + cbx_2__4_ + clb_2__5_ + cbx_2__5_ + clb_2__6_ + cbx_2__6_ + clb_2__7_ + cbx_2__7_ + clb_2__8_ + cbx_2__8_ + sb_2__0_ + cby_2__1_ + sb_2__1_ + cby_2__2_ + sb_2__2_ + cby_2__3_ + sb_2__3_ + cby_2__4_ + sb_2__4_ + cby_2__5_ + sb_2__5_ + cby_2__6_ + sb_2__6_ + cby_2__7_ + sb_2__7_ + cby_2__8_ + sb_2__8_ + cbx_3__0_ + clb_3__1_ + cbx_3__1_ + clb_3__2_ + cbx_3__2_ + clb_3__3_ + cbx_3__3_ + clb_3__4_ + cbx_3__4_ + clb_3__5_ + cbx_3__5_ + clb_3__6_ + cbx_3__6_ + clb_3__7_ + cbx_3__7_ + clb_3__8_ + cbx_3__8_ + sb_3__0_ + cby_3__1_ + sb_3__1_ + cby_3__2_ + sb_3__2_ + cby_3__3_ + sb_3__3_ + cby_3__4_ + sb_3__4_ + cby_3__5_ + sb_3__5_ + cby_3__6_ + sb_3__6_ + cby_3__7_ + sb_3__7_ + cby_3__8_ + sb_3__8_ + cbx_4__0_ + clb_4__1_ + cbx_4__1_ + clb_4__2_ + cbx_4__2_ + clb_4__3_ + cbx_4__3_ + clb_4__4_ + cbx_4__4_ + clb_4__5_ + cbx_4__5_ + clb_4__6_ + cbx_4__6_ + clb_4__7_ + cbx_4__7_ + clb_4__8_ + cbx_4__8_ + sb_4__0_ + cby_4__1_ + sb_4__1_ + cby_4__2_ + sb_4__2_ + cby_4__3_ + sb_4__3_ + cby_4__4_ + sb_4__4_ + cby_4__5_ + sb_4__5_ + cby_4__6_ + sb_4__6_ + cby_4__7_ + sb_4__7_ + cby_4__8_ + sb_4__8_ + cbx_5__0_ + clb_5__1_ + cbx_5__1_ + clb_5__2_ + cbx_5__2_ + clb_5__3_ + cbx_5__3_ + clb_5__4_ + cbx_5__4_ + clb_5__5_ + cbx_5__5_ + clb_5__6_ + cbx_5__6_ + clb_5__7_ + cbx_5__7_ + clb_5__8_ + cbx_5__8_ + sb_5__0_ + cby_5__1_ + sb_5__1_ + cby_5__2_ + sb_5__2_ + cby_5__3_ + sb_5__3_ + cby_5__4_ + sb_5__4_ + cby_5__5_ + sb_5__5_ + cby_5__6_ + sb_5__6_ + cby_5__7_ + sb_5__7_ + cby_5__8_ + sb_5__8_ + cbx_6__0_ + clb_6__1_ + cbx_6__1_ + clb_6__2_ + cbx_6__2_ + clb_6__3_ + cbx_6__3_ + clb_6__4_ + cbx_6__4_ + clb_6__5_ + cbx_6__5_ + clb_6__6_ + cbx_6__6_ + clb_6__7_ + cbx_6__7_ + clb_6__8_ + cbx_6__8_ + sb_6__0_ + cby_6__1_ + sb_6__1_ + cby_6__2_ + sb_6__2_ + cby_6__3_ + sb_6__3_ + cby_6__4_ + sb_6__4_ + cby_6__5_ + sb_6__5_ + cby_6__6_ + sb_6__6_ + cby_6__7_ + sb_6__7_ + cby_6__8_ + sb_6__8_ + cbx_7__0_ + clb_7__1_ + cbx_7__1_ + clb_7__2_ + cbx_7__2_ + clb_7__3_ + cbx_7__3_ + clb_7__4_ + cbx_7__4_ + clb_7__5_ + cbx_7__5_ + clb_7__6_ + cbx_7__6_ + clb_7__7_ + cbx_7__7_ + clb_7__8_ + cbx_7__8_ + sb_7__0_ + cby_7__1_ + sb_7__1_ + cby_7__2_ + sb_7__2_ + cby_7__3_ + sb_7__3_ + cby_7__4_ + sb_7__4_ + cby_7__5_ + sb_7__5_ + cby_7__6_ + sb_7__6_ + cby_7__7_ + sb_7__7_ + cby_7__8_ + sb_7__8_ + cbx_8__0_ + clb_8__1_ + cbx_8__1_ + clb_8__2_ + cbx_8__2_ + clb_8__3_ + cbx_8__3_ + clb_8__4_ + cbx_8__4_ + clb_8__5_ + cbx_8__5_ + clb_8__6_ + cbx_8__6_ + clb_8__7_ + cbx_8__7_ + clb_8__8_ + cbx_8__8_ + sb_8__0_ + cby_8__1_ + sb_8__1_ + cby_8__2_ + sb_8__2_ + cby_8__3_ + sb_8__3_ + cby_8__4_ + sb_8__4_ + cby_8__5_ + sb_8__5_ + cby_8__6_ + sb_8__6_ + cby_8__7_ + sb_8__7_ + cby_8__8_ + sb_8__8_ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Combined Pattern + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve0_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve0_tree.svg new file mode 100644 index 0000000..dd38ee3 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve0_tree.svg @@ -0,0 +1,1049 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sb_0__0_ + cby_0__1_ + sb_0__1_ + cby_0__2_ + sb_0__2_ + cby_0__3_ + sb_0__3_ + cby_0__4_ + sb_0__4_ + cby_0__5_ + sb_0__5_ + cby_0__6_ + sb_0__6_ + cby_0__7_ + sb_0__7_ + cby_0__8_ + sb_0__8_ + cbx_1__0_ + clb_1__1_ + cbx_1__1_ + clb_1__2_ + cbx_1__2_ + clb_1__3_ + cbx_1__3_ + clb_1__4_ + cbx_1__4_ + clb_1__5_ + cbx_1__5_ + clb_1__6_ + cbx_1__6_ + clb_1__7_ + cbx_1__7_ + clb_1__8_ + cbx_1__8_ + sb_1__0_ + cby_1__1_ + sb_1__1_ + cby_1__2_ + sb_1__2_ + cby_1__3_ + sb_1__3_ + cby_1__4_ + sb_1__4_ + cby_1__5_ + sb_1__5_ + cby_1__6_ + sb_1__6_ + cby_1__7_ + sb_1__7_ + cby_1__8_ + sb_1__8_ + cbx_2__0_ + clb_2__1_ + cbx_2__1_ + clb_2__2_ + cbx_2__2_ + clb_2__3_ + cbx_2__3_ + clb_2__4_ + cbx_2__4_ + clb_2__5_ + cbx_2__5_ + clb_2__6_ + cbx_2__6_ + clb_2__7_ + cbx_2__7_ + clb_2__8_ + cbx_2__8_ + sb_2__0_ + cby_2__1_ + sb_2__1_ + cby_2__2_ + sb_2__2_ + cby_2__3_ + sb_2__3_ + cby_2__4_ + sb_2__4_ + cby_2__5_ + sb_2__5_ + cby_2__6_ + sb_2__6_ + cby_2__7_ + sb_2__7_ + cby_2__8_ + sb_2__8_ + cbx_3__0_ + clb_3__1_ + cbx_3__1_ + clb_3__2_ + cbx_3__2_ + clb_3__3_ + cbx_3__3_ + clb_3__4_ + cbx_3__4_ + clb_3__5_ + cbx_3__5_ + clb_3__6_ + cbx_3__6_ + clb_3__7_ + cbx_3__7_ + clb_3__8_ + cbx_3__8_ + sb_3__0_ + cby_3__1_ + sb_3__1_ + cby_3__2_ + sb_3__2_ + cby_3__3_ + sb_3__3_ + cby_3__4_ + sb_3__4_ + cby_3__5_ + sb_3__5_ + cby_3__6_ + sb_3__6_ + cby_3__7_ + sb_3__7_ + cby_3__8_ + sb_3__8_ + cbx_4__0_ + clb_4__1_ + cbx_4__1_ + clb_4__2_ + cbx_4__2_ + clb_4__3_ + cbx_4__3_ + clb_4__4_ + cbx_4__4_ + clb_4__5_ + cbx_4__5_ + clb_4__6_ + cbx_4__6_ + clb_4__7_ + cbx_4__7_ + clb_4__8_ + cbx_4__8_ + sb_4__0_ + cby_4__1_ + sb_4__1_ + cby_4__2_ + sb_4__2_ + cby_4__3_ + sb_4__3_ + cby_4__4_ + sb_4__4_ + cby_4__5_ + sb_4__5_ + cby_4__6_ + sb_4__6_ + cby_4__7_ + sb_4__7_ + cby_4__8_ + sb_4__8_ + cbx_5__0_ + clb_5__1_ + cbx_5__1_ + clb_5__2_ + cbx_5__2_ + clb_5__3_ + cbx_5__3_ + clb_5__4_ + cbx_5__4_ + clb_5__5_ + cbx_5__5_ + clb_5__6_ + cbx_5__6_ + clb_5__7_ + cbx_5__7_ + clb_5__8_ + cbx_5__8_ + sb_5__0_ + cby_5__1_ + sb_5__1_ + cby_5__2_ + sb_5__2_ + cby_5__3_ + sb_5__3_ + cby_5__4_ + sb_5__4_ + cby_5__5_ + sb_5__5_ + cby_5__6_ + sb_5__6_ + cby_5__7_ + sb_5__7_ + cby_5__8_ + sb_5__8_ + cbx_6__0_ + clb_6__1_ + cbx_6__1_ + clb_6__2_ + cbx_6__2_ + clb_6__3_ + cbx_6__3_ + clb_6__4_ + cbx_6__4_ + clb_6__5_ + cbx_6__5_ + clb_6__6_ + cbx_6__6_ + clb_6__7_ + cbx_6__7_ + clb_6__8_ + cbx_6__8_ + sb_6__0_ + cby_6__1_ + sb_6__1_ + cby_6__2_ + sb_6__2_ + cby_6__3_ + sb_6__3_ + cby_6__4_ + sb_6__4_ + cby_6__5_ + sb_6__5_ + cby_6__6_ + sb_6__6_ + cby_6__7_ + sb_6__7_ + cby_6__8_ + sb_6__8_ + cbx_7__0_ + clb_7__1_ + cbx_7__1_ + clb_7__2_ + cbx_7__2_ + clb_7__3_ + cbx_7__3_ + clb_7__4_ + cbx_7__4_ + clb_7__5_ + cbx_7__5_ + clb_7__6_ + cbx_7__6_ + clb_7__7_ + cbx_7__7_ + clb_7__8_ + cbx_7__8_ + sb_7__0_ + cby_7__1_ + sb_7__1_ + cby_7__2_ + sb_7__2_ + cby_7__3_ + sb_7__3_ + cby_7__4_ + sb_7__4_ + cby_7__5_ + sb_7__5_ + cby_7__6_ + sb_7__6_ + cby_7__7_ + sb_7__7_ + cby_7__8_ + sb_7__8_ + cbx_8__0_ + clb_8__1_ + cbx_8__1_ + clb_8__2_ + cbx_8__2_ + clb_8__3_ + cbx_8__3_ + clb_8__4_ + cbx_8__4_ + clb_8__5_ + cbx_8__5_ + clb_8__6_ + cbx_8__6_ + clb_8__7_ + cbx_8__7_ + clb_8__8_ + cbx_8__8_ + sb_8__0_ + cby_8__1_ + sb_8__1_ + cby_8__2_ + sb_8__2_ + cby_8__3_ + sb_8__3_ + cby_8__4_ + sb_8__4_ + cby_8__5_ + sb_8__5_ + cby_8__6_ + sb_8__6_ + cby_8__7_ + sb_8__7_ + cby_8__8_ + sb_8__8_ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L0 Pattern + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve1_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve1_tree.svg new file mode 100644 index 0000000..905f814 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve1_tree.svg @@ -0,0 +1,985 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sb_0__0_ + cby_0__1_ + sb_0__1_ + cby_0__2_ + sb_0__2_ + cby_0__3_ + sb_0__3_ + cby_0__4_ + sb_0__4_ + cby_0__5_ + sb_0__5_ + cby_0__6_ + sb_0__6_ + cby_0__7_ + sb_0__7_ + cby_0__8_ + sb_0__8_ + cbx_1__0_ + clb_1__1_ + cbx_1__1_ + clb_1__2_ + cbx_1__2_ + clb_1__3_ + cbx_1__3_ + clb_1__4_ + cbx_1__4_ + clb_1__5_ + cbx_1__5_ + clb_1__6_ + cbx_1__6_ + clb_1__7_ + cbx_1__7_ + clb_1__8_ + cbx_1__8_ + sb_1__0_ + cby_1__1_ + sb_1__1_ + cby_1__2_ + sb_1__2_ + cby_1__3_ + sb_1__3_ + cby_1__4_ + sb_1__4_ + cby_1__5_ + sb_1__5_ + cby_1__6_ + sb_1__6_ + cby_1__7_ + sb_1__7_ + cby_1__8_ + sb_1__8_ + cbx_2__0_ + clb_2__1_ + cbx_2__1_ + clb_2__2_ + cbx_2__2_ + clb_2__3_ + cbx_2__3_ + clb_2__4_ + cbx_2__4_ + clb_2__5_ + cbx_2__5_ + clb_2__6_ + cbx_2__6_ + clb_2__7_ + cbx_2__7_ + clb_2__8_ + cbx_2__8_ + sb_2__0_ + cby_2__1_ + sb_2__1_ + cby_2__2_ + sb_2__2_ + cby_2__3_ + sb_2__3_ + cby_2__4_ + sb_2__4_ + cby_2__5_ + sb_2__5_ + cby_2__6_ + sb_2__6_ + cby_2__7_ + sb_2__7_ + cby_2__8_ + sb_2__8_ + cbx_3__0_ + clb_3__1_ + cbx_3__1_ + clb_3__2_ + cbx_3__2_ + clb_3__3_ + cbx_3__3_ + clb_3__4_ + cbx_3__4_ + clb_3__5_ + cbx_3__5_ + clb_3__6_ + cbx_3__6_ + clb_3__7_ + cbx_3__7_ + clb_3__8_ + cbx_3__8_ + sb_3__0_ + cby_3__1_ + sb_3__1_ + cby_3__2_ + sb_3__2_ + cby_3__3_ + sb_3__3_ + cby_3__4_ + sb_3__4_ + cby_3__5_ + sb_3__5_ + cby_3__6_ + sb_3__6_ + cby_3__7_ + sb_3__7_ + cby_3__8_ + sb_3__8_ + cbx_4__0_ + clb_4__1_ + cbx_4__1_ + clb_4__2_ + cbx_4__2_ + clb_4__3_ + cbx_4__3_ + clb_4__4_ + cbx_4__4_ + clb_4__5_ + cbx_4__5_ + clb_4__6_ + cbx_4__6_ + clb_4__7_ + cbx_4__7_ + clb_4__8_ + cbx_4__8_ + sb_4__0_ + cby_4__1_ + sb_4__1_ + cby_4__2_ + sb_4__2_ + cby_4__3_ + sb_4__3_ + cby_4__4_ + sb_4__4_ + cby_4__5_ + sb_4__5_ + cby_4__6_ + sb_4__6_ + cby_4__7_ + sb_4__7_ + cby_4__8_ + sb_4__8_ + cbx_5__0_ + clb_5__1_ + cbx_5__1_ + clb_5__2_ + cbx_5__2_ + clb_5__3_ + cbx_5__3_ + clb_5__4_ + cbx_5__4_ + clb_5__5_ + cbx_5__5_ + clb_5__6_ + cbx_5__6_ + clb_5__7_ + cbx_5__7_ + clb_5__8_ + cbx_5__8_ + sb_5__0_ + cby_5__1_ + sb_5__1_ + cby_5__2_ + sb_5__2_ + cby_5__3_ + sb_5__3_ + cby_5__4_ + sb_5__4_ + cby_5__5_ + sb_5__5_ + cby_5__6_ + sb_5__6_ + cby_5__7_ + sb_5__7_ + cby_5__8_ + sb_5__8_ + cbx_6__0_ + clb_6__1_ + cbx_6__1_ + clb_6__2_ + cbx_6__2_ + clb_6__3_ + cbx_6__3_ + clb_6__4_ + cbx_6__4_ + clb_6__5_ + cbx_6__5_ + clb_6__6_ + cbx_6__6_ + clb_6__7_ + cbx_6__7_ + clb_6__8_ + cbx_6__8_ + sb_6__0_ + cby_6__1_ + sb_6__1_ + cby_6__2_ + sb_6__2_ + cby_6__3_ + sb_6__3_ + cby_6__4_ + sb_6__4_ + cby_6__5_ + sb_6__5_ + cby_6__6_ + sb_6__6_ + cby_6__7_ + sb_6__7_ + cby_6__8_ + sb_6__8_ + cbx_7__0_ + clb_7__1_ + cbx_7__1_ + clb_7__2_ + cbx_7__2_ + clb_7__3_ + cbx_7__3_ + clb_7__4_ + cbx_7__4_ + clb_7__5_ + cbx_7__5_ + clb_7__6_ + cbx_7__6_ + clb_7__7_ + cbx_7__7_ + clb_7__8_ + cbx_7__8_ + sb_7__0_ + cby_7__1_ + sb_7__1_ + cby_7__2_ + sb_7__2_ + cby_7__3_ + sb_7__3_ + cby_7__4_ + sb_7__4_ + cby_7__5_ + sb_7__5_ + cby_7__6_ + sb_7__6_ + cby_7__7_ + sb_7__7_ + cby_7__8_ + sb_7__8_ + cbx_8__0_ + clb_8__1_ + cbx_8__1_ + clb_8__2_ + cbx_8__2_ + clb_8__3_ + cbx_8__3_ + clb_8__4_ + cbx_8__4_ + clb_8__5_ + cbx_8__5_ + clb_8__6_ + cbx_8__6_ + clb_8__7_ + cbx_8__7_ + clb_8__8_ + cbx_8__8_ + sb_8__0_ + cby_8__1_ + sb_8__1_ + cby_8__2_ + sb_8__2_ + cby_8__3_ + sb_8__3_ + cby_8__4_ + sb_8__4_ + cby_8__5_ + sb_8__5_ + cby_8__6_ + sb_8__6_ + cby_8__7_ + sb_8__7_ + cby_8__8_ + sb_8__8_ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L1 Pattern + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg new file mode 100644 index 0000000..4f3f389 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_clear_tree.svg @@ -0,0 +1,113 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA88_SOFA_A + + + diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg new file mode 100644 index 0000000..3ee53cd --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_clock0_leve2_tree.svg @@ -0,0 +1,970 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sb_0__0_ + cby_0__1_ + sb_0__1_ + cby_0__2_ + sb_0__2_ + cby_0__3_ + sb_0__3_ + cby_0__4_ + sb_0__4_ + cby_0__5_ + sb_0__5_ + cby_0__6_ + sb_0__6_ + cby_0__7_ + sb_0__7_ + cby_0__8_ + sb_0__8_ + cbx_1__0_ + clb_1__1_ + cbx_1__1_ + clb_1__2_ + cbx_1__2_ + clb_1__3_ + cbx_1__3_ + clb_1__4_ + cbx_1__4_ + clb_1__5_ + cbx_1__5_ + clb_1__6_ + cbx_1__6_ + clb_1__7_ + cbx_1__7_ + clb_1__8_ + cbx_1__8_ + sb_1__0_ + cby_1__1_ + sb_1__1_ + cby_1__2_ + sb_1__2_ + cby_1__3_ + sb_1__3_ + cby_1__4_ + sb_1__4_ + cby_1__5_ + sb_1__5_ + cby_1__6_ + sb_1__6_ + cby_1__7_ + sb_1__7_ + cby_1__8_ + sb_1__8_ + cbx_2__0_ + clb_2__1_ + cbx_2__1_ + clb_2__2_ + cbx_2__2_ + clb_2__3_ + cbx_2__3_ + clb_2__4_ + cbx_2__4_ + clb_2__5_ + cbx_2__5_ + clb_2__6_ + cbx_2__6_ + clb_2__7_ + cbx_2__7_ + clb_2__8_ + cbx_2__8_ + sb_2__0_ + cby_2__1_ + sb_2__1_ + cby_2__2_ + sb_2__2_ + cby_2__3_ + sb_2__3_ + cby_2__4_ + sb_2__4_ + cby_2__5_ + sb_2__5_ + cby_2__6_ + sb_2__6_ + cby_2__7_ + sb_2__7_ + cby_2__8_ + sb_2__8_ + cbx_3__0_ + clb_3__1_ + cbx_3__1_ + clb_3__2_ + cbx_3__2_ + clb_3__3_ + cbx_3__3_ + clb_3__4_ + cbx_3__4_ + clb_3__5_ + cbx_3__5_ + clb_3__6_ + cbx_3__6_ + clb_3__7_ + cbx_3__7_ + clb_3__8_ + cbx_3__8_ + sb_3__0_ + cby_3__1_ + sb_3__1_ + cby_3__2_ + sb_3__2_ + cby_3__3_ + sb_3__3_ + cby_3__4_ + sb_3__4_ + cby_3__5_ + sb_3__5_ + cby_3__6_ + sb_3__6_ + cby_3__7_ + sb_3__7_ + cby_3__8_ + sb_3__8_ + cbx_4__0_ + clb_4__1_ + cbx_4__1_ + clb_4__2_ + cbx_4__2_ + clb_4__3_ + cbx_4__3_ + clb_4__4_ + cbx_4__4_ + clb_4__5_ + cbx_4__5_ + clb_4__6_ + cbx_4__6_ + clb_4__7_ + cbx_4__7_ + clb_4__8_ + cbx_4__8_ + sb_4__0_ + cby_4__1_ + sb_4__1_ + cby_4__2_ + sb_4__2_ + cby_4__3_ + sb_4__3_ + cby_4__4_ + sb_4__4_ + cby_4__5_ + sb_4__5_ + cby_4__6_ + sb_4__6_ + cby_4__7_ + sb_4__7_ + cby_4__8_ + sb_4__8_ + cbx_5__0_ + clb_5__1_ + cbx_5__1_ + clb_5__2_ + cbx_5__2_ + clb_5__3_ + cbx_5__3_ + clb_5__4_ + cbx_5__4_ + clb_5__5_ + cbx_5__5_ + clb_5__6_ + cbx_5__6_ + clb_5__7_ + cbx_5__7_ + clb_5__8_ + cbx_5__8_ + sb_5__0_ + cby_5__1_ + sb_5__1_ + cby_5__2_ + sb_5__2_ + cby_5__3_ + sb_5__3_ + cby_5__4_ + sb_5__4_ + cby_5__5_ + sb_5__5_ + cby_5__6_ + sb_5__6_ + cby_5__7_ + sb_5__7_ + cby_5__8_ + sb_5__8_ + cbx_6__0_ + clb_6__1_ + cbx_6__1_ + clb_6__2_ + cbx_6__2_ + clb_6__3_ + cbx_6__3_ + clb_6__4_ + cbx_6__4_ + clb_6__5_ + cbx_6__5_ + clb_6__6_ + cbx_6__6_ + clb_6__7_ + cbx_6__7_ + clb_6__8_ + cbx_6__8_ + sb_6__0_ + cby_6__1_ + sb_6__1_ + cby_6__2_ + sb_6__2_ + cby_6__3_ + sb_6__3_ + cby_6__4_ + sb_6__4_ + cby_6__5_ + sb_6__5_ + cby_6__6_ + sb_6__6_ + cby_6__7_ + sb_6__7_ + cby_6__8_ + sb_6__8_ + cbx_7__0_ + clb_7__1_ + cbx_7__1_ + clb_7__2_ + cbx_7__2_ + clb_7__3_ + cbx_7__3_ + clb_7__4_ + cbx_7__4_ + clb_7__5_ + cbx_7__5_ + clb_7__6_ + cbx_7__6_ + clb_7__7_ + cbx_7__7_ + clb_7__8_ + cbx_7__8_ + sb_7__0_ + cby_7__1_ + sb_7__1_ + cby_7__2_ + sb_7__2_ + cby_7__3_ + sb_7__3_ + cby_7__4_ + sb_7__4_ + cby_7__5_ + sb_7__5_ + cby_7__6_ + sb_7__6_ + cby_7__7_ + sb_7__7_ + cby_7__8_ + sb_7__8_ + cbx_8__0_ + clb_8__1_ + cbx_8__1_ + clb_8__2_ + cbx_8__2_ + clb_8__3_ + cbx_8__3_ + clb_8__4_ + cbx_8__4_ + clb_8__5_ + cbx_8__5_ + clb_8__6_ + cbx_8__6_ + clb_8__7_ + cbx_8__7_ + clb_8__8_ + cbx_8__8_ + sb_8__0_ + cby_8__1_ + sb_8__1_ + cby_8__2_ + sb_8__2_ + cby_8__3_ + sb_8__3_ + cby_8__4_ + sb_8__4_ + cby_8__5_ + sb_8__5_ + cby_8__6_ + sb_8__6_ + cby_8__7_ + sb_8__7_ + cby_8__8_ + sb_8__8_ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA88_SOFA_A + + +