[HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes

HDL/common/digital_io_behavorial.v

@@ -1,46 +0,0 @@
-//-----------------------------------------------------
-// This file includes behavorial modeling 
-// for digital I/O cells
-// These cells may not be directly used for physical design
-// Synthesis tools may be needed
-//-----------------------------------------------------
-`timescale 1ns/1ps
-
-//-----------------------------------------------------
-// Function    : A minimum input pad
-//-----------------------------------------------------
-module GPIN (
-  inout A, // External PAD signal
-  output Y // Data input
-);
-  assign Y = A;
-endmodule
-
-//-----------------------------------------------------
-// Function    : A minimum output pad
-//-----------------------------------------------------
-module GPOUT (
-  inout Y, // External PAD signal
-  input A // Data output
-);
-  assign Y = A;
-endmodule
-
-//-----------------------------------------------------
-// Function    : A minimum embedded I/O
-//               just an overlay to interface other components
-//-----------------------------------------------------
-module EMBEDDED_IO (
-  input SOC_IN, // Input to drive the inpad signal
-  output SOC_OUT, // Output the outpad signal
-  output SOC_DIR, // Output the directionality
-  output FPGA_IN, // Input data to FPGA
-  input FPGA_OUT, // Output data from FPGA
-  input FPGA_DIR // direction control 
-);
-
-  assign FPGA_IN = SOC_IN;
-  assign SOC_OUT = FPGA_OUT;
-  assign SOC_DIR = FPGA_DIR;
-endmodule
-

HDL/common/digital_io_hd.v

@@ -31,22 +31,26 @@ module EMBEDDED_IO_HD (
   input IO_ISOL_N    // Isolation enable signal
 );
 
-  sky130_fd_sc_hd__and2_0 ISOL_EN_GATE (.A(IO_ISOL_N),
+  wire SOC_DIR_N;
-                                        .B(FPGA_DIR),
+
+  // Use drive-strength 4 for a high fan-out from SoC components
+  sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
+                                        .A(FPGA_DIR),
                                         .X(SOC_DIR)
                                        );
   
   // Use drive-strength 4 for a high fan-out from global routing architecture
-  sky130_fd_sc_hd__and2_4 IN_PROTECT_GATE (.A(SOC_DIR),
+  sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
-                                           .B(SOC_IN),
+  sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
-                                           .X(FPGA_IN)
+                                            .A(SOC_IN),
-                                          );
+                                            .Z(FPGA_IN)
+                                            );
 
   // Use drive-strength 4 for a potential high fan-out from SoC components
-  sky130_fd_sc_hd__and2b_4 OUT_PROTECT_GATE (.A_N(SOC_DIR),
+  sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
-                                             .B(FPGA_OUT),
+                                             .A(FPGA_OUT),
-                                             .X(SOC_OUT)
+                                             .Z(SOC_OUT)
-                                            );
+                                             );
 
 endmodule