From dae7456111d2b5352efff76e404d7ecaddbcf564 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 5 Apr 2021 23:59:21 -0600 Subject: [PATCH] [Flow] QLSOFA Updated flow and ARCH --- .../FPGA1212_QLSOFA_HD_task/BENCHMARK | 1 + .../FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml | 171 ++++++------------ .../config/task_simulation.conf | 35 +++- .../design_variables.yml | 27 ++- .../generate_fabric.openfpga | 16 +- .../generate_testbench.openfpga | 47 ++--- 6 files changed, 148 insertions(+), 149 deletions(-) create mode 120000 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK new file mode 120000 index 0000000..9fed94a --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/BENCHMARK @@ -0,0 +1 @@ +../../BENCHMARK \ No newline at end of file diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml index cb96924..c3f0967 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml @@ -1,5 +1,5 @@ - - - + + + - + - - + 1 1 1 - + 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -306,10 +275,10 @@ - + - + @@ -325,7 +294,7 @@ - + @@ -335,7 +304,7 @@ - + @@ -440,10 +409,10 @@ - - - - + + + + @@ -456,22 +425,22 @@ - - + + - - + + - - + + - - + + @@ -504,18 +473,10 @@ - - 235e-12 - 235e-12 - 235e-12 + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} @@ -523,8 +484,8 @@ - - + + @@ -535,8 +496,8 @@ - - + + @@ -566,20 +527,11 @@ - - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -587,20 +539,21 @@ - - + + + - - + + @@ -622,15 +575,23 @@ - - + + - - + + + + + + - - + + + + + + @@ -652,52 +613,36 @@ I[0] should be connected to in[0] --> - - - - - - - - - - - - - - - - @@ -713,7 +658,7 @@ - + @@ -725,7 +670,7 @@ - + @@ -734,7 +679,7 @@ - + @@ -746,4 +691,4 @@ - \ No newline at end of file + diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf index 66d79ea..2d3bff6 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf @@ -1,4 +1,4 @@ - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs @@ -8,16 +8,17 @@ [GENERAL] run_engine=openfpga_shell -power_analysis = false +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 1*60 +fpga_flow=yosys_vpr arch_variable_file=${PATH:TASK_DIR}/design_variables.yml [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml @@ -28,12 +29,26 @@ openfpga_vpr_route_chan_width=60 arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif +bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v +bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v +bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v +bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v +bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v +bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v +bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act -bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v +bench0_top = and2 +bench1_top = and2_latch +bench2_top = bin2bcd +bench3_top = counter +bench4_top = routing_test +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5_top = rs_decoder_top +bench6_top = top_module +bench7_top = and2_or2 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -vpr_fpga_verilog_formal_verification_top_netlist= +#end_flow_with_test= diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml index dc3d2f3..4c4e441 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/design_variables.yml @@ -1 +1,26 @@ -DELAY_VALUE: 12 \ No newline at end of file +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 0.92e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 +LUT4_DELAY: 1.21e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga index fbab9f3..8e9a0a6 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga @@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose +write_fabric_verilog \ + --file ./SRC \ + --explicit_port_mapping \ + --include_timing \ + --verbose -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench \ + --file ./SRC \ + --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ + --print_top_testbench \ + --print_preconfig_top_testbench \ + --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ + --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here @@ -54,4 +64,4 @@ write_analysis_sdc --file ./SDC_analysis exit # Note : -# To run verification at the end of the flow maintain source in ./SRC directory +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga index 124dbcd..1318a22 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga @@ -1,6 +1,12 @@ -# Run VPR for the 'and' design +# This script is designed to generate Verilog testbenches +# with a fixed device layout +# It will only output netlists to be used by verification tools +# including +# - Verilog testbenches, used by ModelSim +# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime +# #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200 +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -24,11 +30,7 @@ lut_truth_table_fixup # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation @@ -37,28 +39,29 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml - -build_fabric_bitstream +build_architecture_bitstream --verbose --write_file arch_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream -write_fabric_bitstream --format plain_text --file fabric_bitstream.bit -write_fabric_bitstream --format xml --file fabric_bitstream.xml +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists # - Must specify the reference benchmark file if you want to output any testbenches # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc +write_verilog_testbench --file ./SRC \ + --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ + --print_top_testbench \ + --print_preconfig_top_testbench \ + --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ + --explicit_port_mapping +# Exclude signal initialization since it does not help simulator converge +# due to the lack of reset pins for flip-flops +#--include_signal_init # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis @@ -67,4 +70,4 @@ write_analysis_sdc --file ./SDC_analysis exit # Note : -# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file +# To run verification at the end of the flow maintain source in ./SRC directory