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[MSIM] Support pre-pnr simulation in script-run verification

This commit is contained in:
tangxifan 2020-12-06 11:13:50 -07:00
parent 443eb12710
commit da08e505b5
1 changed files with 4 additions and 2 deletions
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6
MSIM/common/run_post_pnr_msim_task.py
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@ -30,6 +30,8 @@ parser.add_argument('--testbench_dir_name', required=True,
help='Specify the directory path for the Verilog testbenches') help='Specify the directory path for the Verilog testbenches')
parser.add_argument('--task_name', required=True, parser.add_argument('--task_name', required=True,
help='Specify the directory path for the Verilog testbenches') help='Specify the directory path for the Verilog testbenches')
parser.add_argument('--testbench_type', default="postpnr",
help='Specify the type of verification: postpnr|prepnr')
args = parser.parse_args() args = parser.parse_args()
##################################################################### #####################################################################
@ -37,7 +39,7 @@ args = parser.parse_args()
##################################################################### #####################################################################
logging.info("Finding testbenches..."); logging.info("Finding testbenches...");
testbench_dir_abspath = abspath(args.testbench_dir_name) + "/postpnr/verilog_testbench"; testbench_dir_abspath = abspath(args.testbench_dir_name) + "/" + args.testbench_type + "/verilog_testbench";
testbench_files = [] testbench_files = []
for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"): for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"):
@ -49,7 +51,7 @@ logging.info("Found " + str(len(testbench_files)) + " testbenches")
# Try to create the directory of Modelsim projects # Try to create the directory of Modelsim projects
##################################################################### #####################################################################
parent_dir_abspath = dirname(dirname(abspath(__file__))) parent_dir_abspath = dirname(dirname(abspath(__file__)))
msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/postpnr/verilog_testbench"; msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/" + args.testbench_type + "/verilog_testbench";
os.makedirs(msim_task_dir_abspath, exist_ok=True) os.makedirs(msim_task_dir_abspath, exist_ok=True)
##################################################################### #####################################################################