From da0469728b98ca7959f87d6d6477a0859152d8f0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Nov 2020 11:50:21 -0700 Subject: [PATCH] [Doc] Add guidelines for setting unuses I/Os --- DOC/source/arch/io_resource.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst index 3557beb..555bde1 100644 --- a/DOC/source/arch/io_resource.rst +++ b/DOC/source/arch/io_resource.rst @@ -57,6 +57,11 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode .. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose. +.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows: + + - all the I/O directionality is set to input mode. + - all the output ports is pulled down to logic ``0`` + .. _fig_fpga_io_map_logic_analyzer_mode: .. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png