diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
new file mode 100644
index 0000000..e27d149
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:85f5b1181ea1f96068bf3cf1400a5e91906d5d03e1f24078af2f22cf337d3985
+size 1381
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..ea37b84
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:7aa52f799ee631d959d1b6c59e8265e9029c8cbe9fe815fd5246080c1250b794
+size 1485
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
new file mode 100644
index 0000000..4f2d3fd
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:feb9721724bd09416b7668d84abf841dcc7805e55c70d098a6edb6601c0f98d3
+size 1377
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..777ac6d
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:983e4841c7ec003427faacb444ac6f70d44f44d42b63da875e66339182a8c81a
+size 1481
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
new file mode 100644
index 0000000..f1189e3
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:b5787e2a130f304b78e0befa5a84943ef0bfe5d95336d1fe01f516fca63f85a8
+size 1369
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..b553d71
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:79dd997c27286dbc5a868f683eca4392b3f04b358d425f02878a63656bf2ddff
+size 1473
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..ac118c1
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:7fc917a8779c191c7e916af5a6341513d7b341b43eee284d0932414c75c08aaf
+size 1321
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..7f1732f
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d6c23fdce319f8b4e5cf60e07d89aaf83b7479fb1076220d13e894e7627d69bd
+size 1495
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v
new file mode 100644
index 0000000..1182769
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1f3a008a9118f5b619a8c0a2f88830fb596db5d0a7d7a4cf8c36f24832e2b216
+size 1375
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..84f9214
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:02e6b21df8939982ee211d8ed61ccb7f6ceb31fa903b2c2c0d9c25971062fb1b
+size 1385
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..96eaa84
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:37c31aee9713b1ec359dd5636668defb6220ab6cc8885eee2810b6b359b4a0f7
+size 1489
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..296749a
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:01cf35ae46aa3f5b4b4f4033461c558876b9317832db844d3ffe841439208e58
+size 1320
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..2a2fd2a
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:003df834b79a1294510fe7f0a081e9a987557f92878eff24bbb28bfb441b4beb
+size 1494