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Merge pull request #10 from LNIS-Projects/xt_dev 

Patch to have UNIQUE routing blocks
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Laboratory for Nano Integrated Systems (LNIS) 2020-11-05 22:23:50 -07:00 committed by GitHub
parent 2ed8bee461 6811604e5c
commit d9cbaa3eec
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1 changed files with 3 additions and 2 deletions
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5
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -140,13 +140,14 @@
<fc_override port_name="regout" fc_type="frac" fc_val="0"/> <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
<fc_override port_name="scin" fc_type="frac" fc_val="0"/> <fc_override port_name="scin" fc_type="frac" fc_val="0"/>
<fc_override port_name="scout" fc_type="frac" fc_val="0"/> <fc_override port_name="scout" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<!--pinlocations pattern="spread"/--> <!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left"></loc> <loc side="left">clb.clk</loc>
<loc side="top">clb.regin clb.scin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc> <loc side="top">clb.regin clb.scin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc> <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.regout clb.scout clb.clk</loc> <loc side="bottom">clb.regout clb.scout</loc>
</pinlocations> </pinlocations>
</tile> </tile>
</tiles> </tiles>