diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index aee247d..2029877 100644 --- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -1,14 +1,14 @@ +This annotation supports the k4_frac_cc_sky130nm.xml +- General purpose logic block +- K = 6, N = 10, I = 40 +- Single mode +- Routing architecture +- L = 4, fc_in = 0.15, fc_out = 0.1 +- Skywater 130nm PDK +- circuit models are binded to the opensource skywater +foundry middle-speed (ms) standard cell library +--> @@ -43,6 +43,18 @@ 10e-12 + + + + + + + 10e-12 + + + 10e-12 + + @@ -67,6 +79,30 @@ 10e-12 + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + @@ -79,6 +115,35 @@ 10e-12 + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + @@ -95,12 +160,12 @@ + OpenFPGA requires the following truth table for the MUX2 + When the select signal sel is enabled, the first input, i.e., in0 + will be propagated to the output, i.e., out + If your standard cell provider does not offer the exact truth table, + you can simply swap the inputs as shown in the example below + --> @@ -118,7 +183,7 @@ - + @@ -127,7 +192,79 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -147,7 +284,6 @@ - @@ -167,33 +303,37 @@ - + - - - + + + + + + - - + + + - + - - - - + + - + + + @@ -207,7 +347,7 @@ - + @@ -228,37 +368,60 @@ - - - - - - + + + + + + + + + + + + + + - - - - - + + + + + + + + - + + + + + + + + + + + + + + - + - - + - + diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 86c2f16..3bdd6bf 100644 --- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -1,27 +1,27 @@ @@ -68,19 +68,28 @@ + If you need to register the I/O, define clocks in the circuit models + These clocks can be handled in back-end + --> - - - + + + + + + + + + + + + - io_top.outpad io_top.inpad + io_top.a2f_o io_top.f2a_i io_top.clk io_top.sc_in io_top.sc_out io_top.reset @@ -88,11 +97,20 @@ - - - + + + + + + + + + + + + - io_right.outpad io_right.inpad + io_right.a2f_o io_right.f2a_i io_right.clk io_right.sc_in io_right.sc_out io_right.reset @@ -100,11 +118,20 @@ - - - + + + + + + + + + + + + - io_bottom.outpad io_bottom.inpad + io_bottom.a2f_o io_bottom.f2a_i io_bottom.clk io_bottom.sc_in io_bottom.sc_out io_bottom.reset @@ -112,11 +139,20 @@ - - - + + + + + + + + + + + + - io_left.outpad io_left.inpad + io_left.a2f_o io_left.f2a_i io_left.clk io_left.sc_in io_left.sc_out io_left.reset @@ -164,7 +200,7 @@ - + @@ -174,7 +210,7 @@ - + @@ -184,7 +220,7 @@ - + @@ -194,30 +230,30 @@ - + + models. We are modifying the delay values however, to include metal C and R, which allows more architecture + experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS + (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of + 45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping + RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately + lined up with Stratix IV. + We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm). + Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm). + The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file + by 2.5x when looking up in Jeff's tables. + The delay values are lined up with Stratix IV, which has an architecture similar to this + proposed FPGA, and which is also 40 nm + C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage + 4x minimum drive strength buffer. --> - + @@ -228,28 +264,28 @@ + book area formula. This means the mux transistors are about 5x minimum drive strength. + We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large + mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume + the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed + by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified + buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive. + I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout + (diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples. + The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by + 2.5x when looking up in Jeff's tables. + Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. + This also leads to the switch being 46% of the total wire delay, which is reasonable. --> - + + With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems + reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> @@ -275,64 +311,131 @@ - - - - + + + + + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + + + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - + + - - - + + + + + + + + + + + + + + + + + + + + + + + - - - + + - + the 4 inputs of fracturable LUT4 are no longer equivalent, + because the 4th input can not be switched when the dual-LUT3 modes are used. + So pin equivalence should be applied to the first 3 inputs only + --> @@ -345,9 +448,9 @@ - @@ -360,7 +463,7 @@ - + @@ -378,7 +481,7 @@ - + @@ -397,7 +500,6 @@ - @@ -416,8 +518,8 @@ - - + + @@ -454,20 +556,20 @@ - + - - + + --> 261e-12 261e-12 @@ -536,13 +638,13 @@ + The global local routing is going to compensate the loss in routability + --> - + in[2]. Such twisted connection is not expected. + I[0] should be connected to in[0] + --> + @@ -550,24 +652,21 @@ + By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, + then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more + naive specification). + --> - - - + + + - - - diff --git a/HDL/common/ql_io_logic.v b/HDL/common/ql_io_logic.v new file mode 100644 index 0000000..e1ed1e1 --- /dev/null +++ b/HDL/common/ql_io_logic.v @@ -0,0 +1,52 @@ +`timescale 1ns/1ps + +//----------------------------------------------------- +// Function : An embedded I/O with +// - An I/O isolation signal to set +// the I/O in input mode. This is to avoid +// any unexpected output signals to damage +// circuits outside the FPGA due to configurable +// memories are not properly initialized +// This feature may not be needed if the configurable +// memory cell has a built-in set/reset functionality +// - Internal protection circuitry to ensure +// clean signals at all the SOC I/O ports +// This is to avoid +// - output any random signal +// when the I/O is in input mode, also avoid +// - driven by any random signal +// when the I/O is output mode +// +// Note: This cell is built with Standard Cells from HD library +// It is already technology mapped and can be directly used +// for physical design +//----------------------------------------------------- +module EMBEDDED_IO_HD ( + input SOC_IN, // Input to drive the inpad signal + output SOC_OUT, // Output the outpad signal + output FPGA_IN, // Input data to FPGA + input FPGA_OUT, // Output data from FPGA + input FPGA_IO_DIR, + input CFG_DONE +); + + wire cfg_done_b; + sky130_fd_sc_hd__inv_1 INV ( + .A(CFG_DONE), + .Y(cfg_done_b) + ); + sky130_fd_sc_hd__or3_1 OR3 ( + .A(FPGA_IO_DIR), + .B(FPGA_OUT), + .C(cfg_done_b), + .X(SOC_OUT) + ); + sky130_fd_sc_hd__and2_1 AND2 ( + .A(FPGA_IO_DIR), + .B(SOC_IN), + .X(FPGA_IN) + ); + + +endmodule + diff --git a/HDL/common/ql_iso_io_logic.v b/HDL/common/ql_iso_io_logic.v new file mode 100644 index 0000000..263898b --- /dev/null +++ b/HDL/common/ql_iso_io_logic.v @@ -0,0 +1,70 @@ +`timescale 1ns/1ps + +//----------------------------------------------------- +// Function : An embedded I/O with +// - An I/O isolation signal to set +// the I/O in input mode. This is to avoid +// any unexpected output signals to damage +// circuits outside the FPGA due to configurable +// memories are not properly initialized +// This feature may not be needed if the configurable +// memory cell has a built-in set/reset functionality +// - Internal protection circuitry to ensure +// clean signals at all the SOC I/O ports +// This is to avoid +// - output any random signal +// when the I/O is in input mode, also avoid +// - driven by any random signal +// when the I/O is output mode +// +// Note: This cell is built with Standard Cells from HD library +// It is already technology mapped and can be directly used +// for physical design +//----------------------------------------------------- +module IO ( + input SOC_IN, // Input to drive the inpad signal + output SOC_OUT, // Output the outpad signal + output FPGA_IN, // Input data to FPGA + input FPGA_OUT, // Output data from FPGA + input FPGA_IO_DIR, + input CFG_DONE, + input IO_ISOL_N +); + + wire cfg_done_b; + wire io_isol; + wire f2a_o_gate; + wire f2a_o_int; + sky130_fd_sc_hd__inv_1 INV_CFG_DONE ( + .A(CFG_DONE), + .Y(cfg_done_b) + ); + sky130_fd_sc_hd__inv_1 INV_ISOL_N ( + .A(IO_ISOL_N), + .Y(io_isol) + ); + // output path + sky130_fd_sc_hd__nor2_1 NOR2 ( + .A(FPGA_IO_DIR), + .B(cfg_done_b), + .Y(f2a_o_gate) + ); + sky130_fd_sc_hd__nand2_1 NAND2 ( + .A(FPGA_OUT), + .B(f2a_o_gate), + .Y(f2a_o_int) + ); + sky130_fd_sc_hd__einvn_4 EINVN_OUT ( + .A(f2a_o_int), + .TE_B(io_isol), + .Z(SOC_OUT) + ); + // input path + sky130_fd_sc_hd__and3_1 AND3 ( + .A(SOC_IN), + .B(FPGA_IO_DIR), + .C(IO_ISOL_N), + .X(FPGA_IN) + ); +endmodule +