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[Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench'

This commit is contained in:
tangxifan 2021-06-09 19:40:41 -06:00
parent 6e99257bed
commit d15e7db1be
3 changed files with 6 additions and 12 deletions
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6
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga
View File

@ -54,11 +54,9 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC \ write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping --explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge # Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops # due to the lack of reset pins for flip-flops

6
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -53,11 +53,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC \ write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping --explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge # Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops # due to the lack of reset pins for flip-flops

6
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -53,11 +53,9 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC \ write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping --explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge # Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops # due to the lack of reset pins for flip-flops