From d0f9ca718d02437875d0706c8f7af588cb41dcde Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 12:47:22 -0700 Subject: [PATCH] [HDL] bug fix in wrapper line generator --- HDL/common/wrapper_lines_generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/HDL/common/wrapper_lines_generator.py b/HDL/common/wrapper_lines_generator.py index 7d2c196..a4808f1 100644 --- a/HDL/common/wrapper_lines_generator.py +++ b/HDL/common/wrapper_lines_generator.py @@ -199,7 +199,7 @@ for pin_info in pin_data['pins']: curr_line = "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(indices[0]) + "_MUX (" \ + ".S(" + pin_data['mode_switch_pin_name'] + "), " \ + ".A1(" + pin_data['caravel_' + pin_info['caravel_pin_type'][1] + '_name'] + "[" + str(indices[2]) + "]), " \ - + ".A0(" + pin_data['caravel_logic_analyzer_input_name'] + str(indices[1]) + "), " \ + + ".A0(" + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "]), " \ + ".X(" + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "])" \ + ");" netlist_lines.append(" " + curr_line + "\n")