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[FPGA1212_v1] Updated the task and PrePNR Verilog netlist

This commit is contained in:
Ganesh Gore 2020-11-27 22:08:16 -07:00
parent da097413b0
commit ce4a6f72f5
38 changed files with 167922 additions and 63881 deletions
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9
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/OpenFPGAEngine.info
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@ -36,6 +36,12 @@ Date: Thu Nov 12 19:43:43 2020 -0700
On branch master
Your branch is up to date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: openfpga_flow/scripts/run_fpga_flow.py
modified: openfpga_flow/scripts/run_fpga_task.py
Untracked files:
(use "git add <file>..." to include in what will be committed)
openfpga/openfpga
@ -57,9 +63,10 @@ Untracked files:
openfpga_flow/tasks/FPGA44_FLAT_task
openfpga_flow/tasks/FPGA6464_FLAT_task
openfpga_flow/tasks/FPGA66_FLAT_task
openfpga_flow/tasks/FPGA88_FLAT_HD_SKY_task
openfpga_flow/tasks/FPGA88_FLAT_task
openfpga_flow/tasks/routing_test/
openfpga_flow/tasks/skywater_openfpga_task
vpr/vpr
nothing added to commit but untracked files present (use "git add" to track)
no changes added to commit (use "git add" and/or "git commit -a")

33
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
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@ -59,7 +59,6 @@ wire [0:0] fabric_sc_out;
//
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
@ -75,12 +74,16 @@ wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_ff_1_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:0] mux_tree_size2_3_out;
wire [0:1] mux_tree_size2_3_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_size2_mem_2_ccff_tail;
//
//
@ -103,10 +106,10 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en[0]),
.ff_D(direct_interc_8_out[0]),
.ff_DI(direct_interc_9_out[0]),
.ff_D(mux_tree_size2_3_out[0]),
.ff_DI(direct_interc_8_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.ff_clk(direct_interc_10_out[0]));
.ff_clk(direct_interc_9_out[0]));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
@ -126,6 +129,12 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out[0]));
mux_tree_size2 mux_ff_1_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]}),
.sram(mux_tree_size2_3_sram[0:1]),
.sram_inv(mux_ff_1_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_3_out[0]));
mux_tree_size2_mem mem_fabric_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
@ -141,9 +150,15 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
mux_tree_size2_mem mem_ff_0_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_size2_2_sram[0:1]));
mux_tree_size2_mem mem_ff_1_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_3_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_reg_out[0]));
@ -177,16 +192,12 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail;
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]),
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fabric_clk[0]),
.out(direct_interc_10_out[0]));
.out(direct_interc_9_out[0]));
endmodule
//

5
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/routing/sb_0__2_.v
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@ -1,7 +1,7 @@
module sb_0__2_
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, prog_clk_0_E_in );
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, prog_clk_0_E_in );
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
@ -20,8 +20,6 @@ module sb_0__2_
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input prog_clk_0_E_in;
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
@ -114,7 +112,6 @@ module sb_0__2_
assign chany_bottom_out[1] = chanx_right_in[17];
assign chany_bottom_out[19] = chanx_right_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6

9
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/routing/sb_2__2_.v
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@ -1,7 +1,7 @@
module sb_2__2_
( chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, prog_clk_0_S_in );
( chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_BOT, SC_OUT_BOT, prog_clk_0_S_in );
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
@ -26,10 +26,8 @@ module sb_2__2_
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
input prog_clk_0_S_in;
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
@ -143,8 +141,7 @@ module sb_2__2_
assign chany_bottom_out[16] = chanx_left_in[17];
assign chany_bottom_out[17] = chanx_left_in[18];
assign chany_bottom_out[18] = chanx_left_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign SC_OUT_BOT = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6

2
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/fpga_top.v
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@ -73,7 +73,7 @@ module fpga_top (
//
//
//
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b));
//
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];

2306
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_autocheck_top_tb.v
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2304
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_top_formal_verification.v
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2
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit
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132076
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml
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19586
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
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67960
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/Testbench_Case/case_top.tcl Normal file
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86
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/openfpgashell.log
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@ -67,25 +67,25 @@ Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
# Building complex block graph
Warning 6: [LINE 586] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 586] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 592] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 592] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 598] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 598] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 604] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 604] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 610] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 610] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 616] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 616] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 622] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 622] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 628] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 628] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
Warning 6: [LINE 593] false logically-equivalent pin clb[0].I0[1].
Warning 7: [LINE 593] false logically-equivalent pin clb[0].I0[2].
Warning 8: [LINE 599] false logically-equivalent pin clb[0].I1[1].
Warning 9: [LINE 599] false logically-equivalent pin clb[0].I1[2].
Warning 10: [LINE 605] false logically-equivalent pin clb[0].I2[1].
Warning 11: [LINE 605] false logically-equivalent pin clb[0].I2[2].
Warning 12: [LINE 611] false logically-equivalent pin clb[0].I3[1].
Warning 13: [LINE 611] false logically-equivalent pin clb[0].I3[2].
Warning 14: [LINE 617] false logically-equivalent pin clb[0].I4[1].
Warning 15: [LINE 617] false logically-equivalent pin clb[0].I4[2].
Warning 16: [LINE 623] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 623] false logically-equivalent pin clb[0].I5[2].
Warning 18: [LINE 629] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 629] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 635] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 635] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.01 seconds (max_rss 9.7 MiB, delta_rss +0.7 MiB)
# Load circuit
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.2 MiB)
# Clean circuit
Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred 0 additional primitive pins as constant generators due to constant inputs
@ -257,7 +257,7 @@ Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.02 seconds).
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.02 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
# Load Packing took 0.02 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB)
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
Netlist num_nets: 3
@ -329,10 +329,10 @@ Warning 60: in check_rr_node: RR node: 1389 type: OPIN location: (11,1) pin: 50
Warning 61: in check_rr_node: RR node: 1390 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 62: in check_rr_node: RR node: 1479 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 63: in check_rr_node: RR node: 1480 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.16 seconds (max_rss 18.0 MiB, delta_rss +7.3 MiB)
## Build tileable routing resource graph took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
RR Graph Nodes: 18580
RR Graph Edges: 96524
# Create Device took 0.16 seconds (max_rss 18.0 MiB, delta_rss +7.3 MiB)
# Create Device took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
# Placement
## Computing placement delta delay look-up
@ -654,7 +654,7 @@ Setup slack histogram:
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
Timing analysis took 0.000515351 seconds (0.000458161 STA, 5.719e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined).
Timing analysis took 0.000513075 seconds (0.000459398 STA, 5.3677e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined).
VPR suceeded
The entire flow of VPR took 0.50 seconds (max_rss 19.5 MiB)
@ -886,7 +886,7 @@ Done with 19 nodes mapping
[99%] Backannotated GSB[12][11]
[100%] Backannotated GSB[12][12]
Backannotated 169 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[0%] Sorted edges for GSB[0][0]
[1%] Sorted edges for GSB[0][1]
@ -1127,13 +1127,13 @@ Building physical tiles...Done
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 27.1 MiB, delta_rss +0.5 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.10 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB)
## Add module nets between grids and GSBs took 0.14 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 43.3 MiB, delta_rss +0.5 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.01 seconds (max_rss 44.6 MiB, delta_rss +1.0 MiB)
# Build FPGA fabric module took 0.13 seconds (max_rss 44.6 MiB, delta_rss +20.6 MiB)
Build fabric module graph took 0.14 seconds (max_rss 44.6 MiB, delta_rss +23.7 MiB)
## Add module nets for configuration buses took 0.02 seconds (max_rss 44.6 MiB, delta_rss +1.0 MiB)
# Build FPGA fabric module took 0.17 seconds (max_rss 44.6 MiB, delta_rss +20.6 MiB)
Build fabric module graph took 0.19 seconds (max_rss 44.6 MiB, delta_rss +23.7 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
Create global port info for top module
@ -1168,10 +1168,10 @@ Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done
Build fabric-independent bitstream for implementation 'top'
took 0.11 seconds (max_rss 49.4 MiB, delta_rss +4.8 MiB)
took 0.16 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB)
Warning 116: Directory path is empty and nothing will be created.
Write 65656 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 65656 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.62 seconds (max_rss 49.4 MiB, delta_rss +0.0 MiB)
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.52 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB)
Command line to execute: build_fabric_bitstream
@ -1182,7 +1182,7 @@ Build fabric dependent bitstream
Build fabric dependent bitstream
took 0.03 seconds (max_rss 53.3 MiB, delta_rss +3.9 MiB)
took 0.03 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB)
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
@ -1191,8 +1191,8 @@ Confirm selected options when call command 'write_fabric_bitstream':
--format: plain_text
--verbose: off
Warning 117: Directory path is empty and nothing will be created.
Write 65656 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 65656 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 53.3 MiB, delta_rss +0.0 MiB)
Write 67960 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 67960 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
@ -1201,8 +1201,8 @@ Confirm selected options when call command 'write_fabric_bitstream':
--format: xml
--verbose: off
Warning 118: Directory path is empty and nothing will be created.
Write 65656 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 65656 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.10 seconds (max_rss 53.3 MiB, delta_rss +0.0 MiB)
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.09 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
@ -1264,7 +1264,7 @@ Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 71 Verilog modules in total
Write Verilog netlists for FPGA fabric
took 0.49 seconds (max_rss 56.2 MiB, delta_rss +2.9 MiB)
took 0.34 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
@ -1284,17 +1284,17 @@ Write Verilog testbenches for FPGA fabric
Warning 120: Directory './SRC' already exists. Will overwrite contents
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.18 seconds (max_rss 56.2 MiB, delta_rss +0.0 MiB)
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.11 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.2 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
Will use 65657 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.19 seconds (max_rss 56.3 MiB, delta_rss +0.1 MiB)
Will use 67961 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.12 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB)
Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 56.3 MiB, delta_rss +0.0 MiB)
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 56.6 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric
took 0.39 seconds (max_rss 56.3 MiB, delta_rss +0.1 MiB)
took 0.24 seconds (max_rss 56.7 MiB, delta_rss +0.3 MiB)
Command line to execute: exit
@ -1302,6 +1302,6 @@ Confirm selected options when call command 'exit':
Finish execution with 0 errors
The entire OpenFPGA flow took 2.37 seconds
The entire OpenFPGA flow took 2.06 seconds
Thank you for using OpenFPGA!

36
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__0__scandef.def Normal file
View File

@ -0,0 +1,36 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__1__scandef.def Normal file
View File

@ -0,0 +1,64 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__2__scandef.def Normal file
View File

@ -0,0 +1,64 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

4
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_0__1__scandef.def Normal file
View File

@ -0,0 +1,4 @@
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_1__1__scandef.def Normal file
View File

@ -0,0 +1,64 @@
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_2__1__scandef.def Normal file
View File

@ -0,0 +1,64 @@
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

1152
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/grid_clb_scandef.def Normal file
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File diff suppressed because it is too large Load Diff

52
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_0__0__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_1_

88
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_0__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_

88
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_0__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_

85
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_1__0__scandef.def Normal file
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@ -0,0 +1,85 @@
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_1__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_1__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

85
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_2__0__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_2__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/sb_2__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

1
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/arch/openfpga_arch.xml
View File

@ -221,6 +221,7 @@
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>

15
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/arch/vpr_arch.xml
View File

@ -396,18 +396,21 @@
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux3" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
@ -551,6 +554,7 @@
<mode name="shift_register">
<pb_type name="shift_reg" num_pb="1">
<input name="reg_in" num_pins="1"/>
<output name="ff_out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
@ -564,13 +568,16 @@
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.reg_in" output="shift_reg.reg_in"/>
<direct name="direct2" input="shift_reg.reg_out" output="fle.reg_out"/>
<direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
<direct name="direct3" input="shift_reg.ff_out" output="fle.out"/>
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
</interconnect>
</mode>
<!-- Define shift register end -->

2
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/config/task.conf
View File

@ -13,6 +13,8 @@ spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga

2
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/config/task_generation.conf
View File

@ -13,6 +13,8 @@ spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga

1
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/design_variables.yml Normal file
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@ -0,0 +1 @@
DELAY_VALUE: 12

71
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/expand_sdc.py
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@ -1,71 +0,0 @@
import yaml
import argparse
import pprint as pp
import glob
import os
def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60)
parser = argparse.ArgumentParser(formatter_class=formatter)
# Mandatory arguments
parser.add_argument('--hierfile', type=str, default="design.hier")
parser.add_argument('--shellscript_name', type=str, default="sdc_expand.sh")
parser.add_argument('--in_dir', type=str, default="./sdc/")
parser.add_argument('--out_dir', type=str, default="./sdc/expanded")
parser.add_argument('--extract_format', type=str, default="tcl")
parser.add_argument('--compress', type=bool, default=False)
args = parser.parse_args()
print(f"In_dir = {args.in_dir}")
print(f"Out_dir = {args.out_dir}")
if args.extract_format == "sdc":
with open(args.hierfile) as f:
with open(args.shellscript_name, 'w') as fp:
designHier = yaml.load(f, Loader=yaml.FullLoader)
for eachHier in designHier:
for eachMod, instanceList in eachHier.items():
fp.write(f"mkdir -p {eachMod}\n")
for eachInst in instanceList:
eachInst = eachInst.replace("/", "_")
st = (f"sed \"s/{eachMod}/{eachInst}/g\" {args.in_dir}/{eachMod}.sdc " +
f"> {args.out_dir}/{eachInst}/{eachInst}.sdc\n")
fp.write(st)
if args.compress:
fp.write(f"tar -zcvf {args.out_dir}/{eachMod}.tar.gz "
f"{args.out_dir}/{eachInst}/")
elif args.extract_format == "tcl":
files = glob.glob(os.path.join(args.in_dir, 'grid*.txt'))
filename = files[0]
print(f"Reading {filename}")
with open(filename) as f:
with open(args.shellscript_name, 'w') as fp:
designHier = yaml.load(f, Loader=yaml.FullLoader)[:5]
for eachModule in designHier:
ForLoopStruct = []
while True:
instList = eachModule[list(eachModule.keys())[0]]
iterAgain = all([isinstance(ele, str) for ele in instList])
if (iterAgain):
# print(list(eachModule.keys())[0])
# print(f">> leaf Instance {instList}")
ForLoopStruct.append({
list(eachModule.keys())[0]:
instList
})
break
else:
ForLoopStruct.append({
list(eachModule.keys())[0]:
[list(ee.keys())[0] for ee in instList]
})
# print(list(eachModule.keys())[0])
# print([list(ee.keys())[0] for ee in instList])
eachModule = instList[0]
del ForLoopStruct[1::2]
print("= = "*10)
print("ForLoop Struct")
pp.pprint(ForLoopStruct)
print("= = "*10)

46
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/process_top_def.sh Normal file
View File

@ -0,0 +1,46 @@
#!/bin/bash
cp user_project_wrapper_template.def user_project_wrapper_empty.def
sed -i '/^SPECIALNETS/,/END SPECIALNETS/d' user_project_wrapper_empty.def
sed -i '/^VIAS/,/END VIAS/d' user_project_wrapper_empty.def
sed -i '/^ROW ROW/d' user_project_wrapper_empty.def
sed -i '/^TRACKS/d' user_project_wrapper_empty.def
sed -i 's/user_project_wrapper/fpga_top/' user_project_wrapper_empty.def
VDD_LINES=$(grep "\- vdda\|vccd" user_project_wrapper_empty.def)
VSS_LINES=$(grep "\- vssa\|vssd" user_project_wrapper_empty.def)
sed -i '/^ - v.*$/d' user_project_wrapper_empty.def
X="2920000"
Y="3520000"
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
sed -i '/END PINS/d' user_project_wrapper_empty.def
sed -i '/END DESIGN/d' user_project_wrapper_empty.def
echo " - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER" >> user_project_wrapper_empty.def
printf "${VDD_LINES} ;\n" >> user_project_wrapper_empty.def
echo "- VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND" >> user_project_wrapper_empty.def
printf "${VSS_LINES} ;\n" >> user_project_wrapper_empty.def
echo "END PINS" >> user_project_wrapper_empty.def
echo "END DESIGN" >> user_project_wrapper_empty.def

2
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/sc_verilog/fpga_top.v
View File

@ -73,7 +73,7 @@ module fpga_top (
//
//
//
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b));
//
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];

1219
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/user_project_wrapper_empty.def Normal file
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3768
FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/user_project_wrapper_template.def Normal file
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