From cbe50535ca1d50f68dd0c1ba95bff23a3fb15b72 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Mon, 28 Dec 2020 08:35:17 -0800 Subject: [PATCH] further changes in architecture to make io interfaces routable --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 12 +- BENCHMARK/io_tc1/rtl/demux.v | 106 ++++++++++++++++++ BENCHMARK/io_tc1/rtl/io_tc1.v | 11 ++ BENCHMARK/io_tc1/rtl/mux.v | 104 +++++++++++++++++ .../config/task_template.conf | 2 + 5 files changed, 229 insertions(+), 6 deletions(-) create mode 100644 BENCHMARK/io_tc1/rtl/demux.v create mode 100644 BENCHMARK/io_tc1/rtl/io_tc1.v create mode 100644 BENCHMARK/io_tc1/rtl/mux.v diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index b694e3e..126aa88 100644 --- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -72,7 +72,7 @@ These clocks can be handled in back-end --> - + @@ -84,7 +84,7 @@ - + @@ -96,7 +96,7 @@ - + @@ -108,7 +108,7 @@ - + @@ -250,7 +250,7 @@ With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> - + 1 1 1 @@ -260,7 +260,7 @@ 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 diff --git a/BENCHMARK/io_tc1/rtl/demux.v b/BENCHMARK/io_tc1/rtl/demux.v new file mode 100644 index 0000000..21c0dee --- /dev/null +++ b/BENCHMARK/io_tc1/rtl/demux.v @@ -0,0 +1,106 @@ +module demux_1x512 (in,sel,out); +input in; +input [8:0] sel; +output [511:0] out; +wire [1:0] out_w; + +demux_1x2 d512_0(.in(in),.sel(sel[8]),.out(out_w[1:0])); +demux_1x256 d512_1(.in(out_w[0]),.sel(sel[7:0]),.out(out[255:0])); +demux_1x256 d512_2(.in(out_w[1]),.sel(sel[7:0]),.out(out[511:256])); + +endmodule + +module demux_1x256 (in,sel,out); +input in; +input [7:0] sel; +output [255:0] out; +wire [1:0] out_w; + +demux_1x2 d256_0(.in(in),.sel(sel[7]),.out(out_w[1:0])); +demux_1x128 d256_1(.in(out_w[0]),.sel(sel[6:0]),.out(out[127:0])); +demux_1x128 d256_2(.in(out_w[1]),.sel(sel[6:0]),.out(out[255:128])); + +endmodule + +module demux_1x128 (in,sel,out); +input in; +input [6:0] sel; +output [127:0] out; +wire [1:0] out_w; + +demux_1x2 d128_0(.in(in),.sel(sel[6]),.out(out_w[1:0])); +demux_1x64 d128_1(.in(out_w[0]),.sel(sel[5:0]),.out(out[63:0])); +demux_1x64 d128_2(.in(out_w[1]),.sel(sel[5:0]),.out(out[127:64])); + +endmodule + +module demux_1x64 (in,sel,out); +input in; +input [5:0] sel; +output [63:0] out; +wire [1:0] out_w; + +demux_1x2 d64_0(.in(in),.sel(sel[5]),.out(out_w[1:0])); +demux_1x32 d64_1(.in(out_w[0]),.sel(sel[4:0]),.out(out[31:0])); +demux_1x32 d64_2(.in(out_w[1]),.sel(sel[4:0]),.out(out[63:32])); + +endmodule + +module demux_1x32 (in,sel,out); +input in; +input [4:0] sel; +output [31:0] out; +wire [1:0] out_w; + +demux_1x2 d32_0(.in(in),.sel(sel[4]),.out(out_w[1:0])); +demux_1x16 d32_1(.in(out_w[0]),.sel(sel[3:0]),.out(out[15:0])); +demux_1x16 d32_2(.in(out_w[1]),.sel(sel[3:0]),.out(out[31:16])); + +endmodule + + +module demux_1x16 (in,sel,out); +input in; +input [3:0] sel; +output [15:0] out; +wire [1:0] out_w; + +demux_1x2 d16_0(.in(in),.sel(sel[3]),.out(out_w[1:0])); +demux_1x8 d16_1(.in(out_w[0]),.sel(sel[2:0]),.out(out[7:0])); +demux_1x8 d16_2(.in(out_w[1]),.sel(sel[2:0]),.out(out[15:8])); + +endmodule + +module demux_1x8 (in,sel,out); +input in; +input [2:0] sel; +output [7:0] out; +wire [1:0] out_w; + +demux_1x2 d8_0(.in(in),.sel(sel[2]),.out(out_w[1:0])); +demux_1x4 d8_1(.in(out_w[0]),.sel(sel[1:0]),.out(out[3:0])); +demux_1x4 d8_2(.in(out_w[1]),.sel(sel[1:0]),.out(out[7:4])); + +endmodule + +module demux_1x4 (in,sel,out); +input in; +input [1:0] sel; +output [3:0] out; +wire [1:0]out_w; + +demux_1x2 d4_0(.in(in),.sel(sel[1]),.out(out_w)); +demux_1x2 d4_1(.in(out_w[0]),.sel(sel[0]),.out(out[1:0])); +demux_1x2 d4_2(.in(out_w[1]),.sel(sel[0]),.out(out[3:2])); + + +endmodule + +module demux_1x2 (in,sel,out); +input in,sel; +output [1:0] out; + +assign out[0] = (sel==0) ? in :0; +assign out[1] = (sel==1) ? in :0; + +endmodule \ No newline at end of file diff --git a/BENCHMARK/io_tc1/rtl/io_tc1.v b/BENCHMARK/io_tc1/rtl/io_tc1.v new file mode 100644 index 0000000..b9fdcf1 --- /dev/null +++ b/BENCHMARK/io_tc1/rtl/io_tc1.v @@ -0,0 +1,11 @@ +module io_tc1 (mux_in, demux_out,mux_sel, demux_sel); +input [0:511] mux_in; +input [8:0]mux_sel; +input [8:0]demux_sel; +output [511:0]demux_out; + +mux_512x1 mux0 (.in(mux_in),.sel(mux_sel),.out(mux_out)); +demux_1x512 demux0 (.in(mux_out),.sel(demux_sel),.out(demux_out)); + +endmodule + diff --git a/BENCHMARK/io_tc1/rtl/mux.v b/BENCHMARK/io_tc1/rtl/mux.v new file mode 100644 index 0000000..6948567 --- /dev/null +++ b/BENCHMARK/io_tc1/rtl/mux.v @@ -0,0 +1,104 @@ +module mux_512x1 (in,sel,out); +input [511:0] in; +input [8:0]sel; +output out; +wire out0_w, out1_w; + +mux_256x1 m512_0(.in(in[255:0]),.sel(sel[7:0]),.out(out0_w)); +mux_256x1 m512_1(.in(in[511:256]),.sel(sel[7:0]),.out(out1_w)); +mux_2x1 m512_2(.a(out0_w),.b(out1_w),.sel(sel[8]),.out(out)); + +endmodule + +module mux_256x1 (in,sel,out); +input [255:0] in; +input [7:0]sel; +output out; +wire out0_w, out1_w; + +mux_128x1 m256_0(.in(in[127:0]),.sel(sel[6:0]),.out(out0_w)); +mux_128x1 m256_1(.in(in[255:128]),.sel(sel[6:0]),.out(out1_w)); +mux_2x1 m256_2(.a(out0_w),.b(out1_w),.sel(sel[7]),.out(out)); + +endmodule + +module mux_128x1 (in,sel,out); +input [127:0] in; +input [6:0]sel; +output out; +wire out0_w, out1_w; + +mux_64x1 m128_0(.in(in[63:0]),.sel(sel[5:0]),.out(out0_w)); +mux_64x1 m128_1(.in(in[127:64]),.sel(sel[5:0]),.out(out1_w)); +mux_2x1 m128_2(.a(out0_w),.b(out1_w),.sel(sel[6]),.out(out)); + +endmodule + +module mux_64x1 (in,sel,out); +input [63:0] in; +input [5:0]sel; +output out; +wire out0_w, out1_w; + +mux_32x1 m64_0(.in(in[31:0]),.sel(sel[4:0]),.out(out0_w)); +mux_32x1 m64_1(.in(in[63:32]),.sel(sel[4:0]),.out(out1_w)); +mux_2x1 m64_2(.a(out0_w),.b(out1_w),.sel(sel[5]),.out(out)); + +endmodule + +module mux_32x1 (in,sel,out); +input [31:0] in; +input [4:0]sel; +output out; +wire out0_w, out1_w; + +mux_16x1 m32_0(.in(in[15:0]),.sel(sel[3:0]),.out(out0_w)); +mux_16x1 m32_1(.in(in[31:16]),.sel(sel[3:0]),.out(out1_w)); +mux_2x1 m32_2(.a(out0_w),.b(out1_w),.sel(sel[4]),.out(out)); + +endmodule + +module mux_16x1 (in,sel,out); +input [15:0] in; +input [3:0]sel; +output out; +wire out0_w, out1_w; + +mux_8x1 m16_0(.in(in[7:0]),.sel(sel[2:0]),.out(out0_w)); +mux_8x1 m16_1(.in(in[15:8]),.sel(sel[2:0]),.out(out1_w)); +mux_2x1 m16_2(.a(out0_w),.b(out1_w),.sel(sel[3]),.out(out)); + +endmodule + +module mux_8x1 (in,sel,out); +input [7:0] in; +input [2:0]sel; +output out; +wire out0_w, out1_w; + +mux_4x1 m8_0(.in(in[3:0]),.sel(sel[1:0]),.out(out0_w)); +mux_4x1 m8_1(.in(in[7:4]),.sel(sel[1:0]),.out(out1_w)); +mux_2x1 m8_2(.a(out0_w),.b(out1_w),.sel(sel[2]),.out(out)); + +endmodule + +module mux_4x1 (in,sel,out); +input [3:0] in; +input [1:0]sel; +output out; +wire out0_w, out1_w; + +mux_2x1 m4_0(.a(in[0]),.b(in[1]),.sel(sel[0]),.out(out0_w)); +mux_2x1 m4_1(.a(in[2]),.b(in[3]),.sel(sel[0]),.out(out1_w)); +mux_2x1 m4_2(.a(out0_w),.b(out1_w),.sel(sel[1]),.out(out)); + +endmodule + +module mux_2x1 (a,b,sel,out); +input a,b; +input sel; +output out; + +assign out = sel ? b : a; + +endmodule \ No newline at end of file diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf index 84fe134..154378a 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf @@ -52,6 +52,7 @@ bench18=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/multi_enc_decx2x4/rtl/*.v #bench19=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sdc_controller/rtl/*.v bench20=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sha256/rtl/*.v bench21=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/unsigned_mult_80/rtl/*.v +bench22=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_tc1/rtl/*.v [SYNTHESIS_PARAM] bench0_top = and2 @@ -77,6 +78,7 @@ bench18_top = multi_enc_decx2x4 #bench19_top = sdc_controller bench20_top = sha256 bench21_top = unsigned_mult_80 +bench22_top = io_tc1 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test=