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[HDL] Bug fix due to custom cell name changing

This commit is contained in:
tangxifan 2020-12-18 20:24:55 -07:00
parent 1eac22feba
commit c523d968c7
1 changed files with 2 additions and 2 deletions
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4
HDL/common/fd_hd_mux_custom_cells_tt.v
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@ -3,7 +3,7 @@
// type: scs8hd_muxinv8_1 // type: scs8hd_muxinv8_1
`timescale 1ns/10ps `timescale 1ns/10ps
`celldefine `celldefine
module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B); module sky130_uuopenfpga_cc_hd_invmux2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
output Z; output Z;
input Q1, Q2, S0, S0B, S1, S1B; input Q1, Q2, S0, S0B, S1, S1B;
@ -36,7 +36,7 @@ endmodule
// type: scs8hd_muxinv8_1 // type: scs8hd_muxinv8_1
`timescale 1ns/10ps `timescale 1ns/10ps
`celldefine `celldefine
module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B); module sky130_uuopenfpga_cc_hd_invmux3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
output Z; output Z;
input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B; input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B;