diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
new file mode 100644
index 0000000..f675a59
--- /dev/null
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
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+ io_top.outpad io_top.inpad
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+ io_right.outpad io_right.inpad
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+ io_bottom.outpad io_bottom.inpad
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+ io_left.outpad io_left.inpad
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+ clb.clk clb.reset
+ clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
+ clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
+ clb.reg_out clb.sc_out clb.cout
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diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga
new file mode 100644
index 0000000..8cfc694
--- /dev/null
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga
@@ -0,0 +1,74 @@
+# This script is designed to generate Verilog testbenches
+# with a fixed device layout
+# It will only output netlists to be used by verification tools
+# including
+# - Verilog testbenches, used by ModelSim
+# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
+#
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --absorb_buffer_luts off --power
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+# - Enabled compression on routing architecture modules
+# - Enable pin duplication on grid modules
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+# - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file arch_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
+# Write the Verilog testbench for FPGA fabric
+# - We suggest the use of same output directory as fabric Verilog netlists
+# - Must specify the reference benchmark file if you want to output any testbenches
+# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
+ --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
+ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
+ --print_top_testbench \
+# --print_preconfig_top_testbench \ disabled for now due to disk space limitation on github actions
+ --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
+ --explicit_port_mapping
+# Exclude signal initialization since it does not help simulator converge
+# due to the lack of reset pins for flip-flops
+#--include_signal_init
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml
new file mode 100644
index 0000000..d9f8401
--- /dev/null
+++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml
@@ -0,0 +1,48 @@
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