From bff4fdfdc125e422552328551d63c7ac6c829331 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 2 Nov 2020 11:27:44 -0700 Subject: [PATCH] [Arch] Update pin equivalence for the non-LR non-adder k4 arch --- ...n_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +- ...egister_scan_chain_nonLR_skywater130nm.xml | 126 ++++++++++++------ 2 files changed, 83 insertions(+), 45 deletions(-) diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml index 806c518..e4b1313 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml @@ -174,7 +174,7 @@ - + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml index 5d865fd..1d28d35 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml @@ -78,14 +78,22 @@ - - - - - - - - + + + + + + + + + + + + + + + + @@ -102,8 +110,8 @@ clb.clk clb.regin clb.scin - clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3 - clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7 + clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i @@ -276,24 +284,28 @@ - + - - - - - - - - + + + + + + + + + + + + + + + + @@ -534,30 +546,56 @@ - - + + + - + + - + + - + + - + + - + + - + + - + + + + + + + + + + + + + + + + + + + + + + + + + +