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[Documentation] Update frontpage README for guidelines

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tangxifan 2020-10-14 09:50:37 -06:00
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# skywater-openfpga # skywater-openfpga
FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
## Quick Start
```bash
#Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/skywater-openfpga.git
python3 SCRIPT/repo_setup.py
```
* Keep this folder clean and organized as follows * Keep this folder clean and organized as follows
- **DOC**: documentation of the project - **DOC**: documentation of the project
- **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists - **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists