diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
deleted file mode 100644
index be0309b..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
deleted file mode 100644
index bce7666..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
+++ /dev/null
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
deleted file mode 100644
index 915e1b7..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
deleted file mode 100644
index c7485a1..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
deleted file mode 100644
index 57ca9fa..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
+++ /dev/null
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
deleted file mode 100644
index 1f341b1..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
+++ /dev/null
@@ -1,269 +0,0 @@
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
deleted file mode 100644
index ee61144..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ /dev/null
@@ -1,250 +0,0 @@
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
deleted file mode 100644
index c372a49..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ /dev/null
@@ -1,255 +0,0 @@
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diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
deleted file mode 100644
index e574bd8..0000000
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml
+++ /dev/null
@@ -1,737 +0,0 @@
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- clb.cout clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7
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diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
deleted file mode 100644
index 4a0f049..0000000
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+++ /dev/null
@@ -1,646 +0,0 @@
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- clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
- clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
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diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
deleted file mode 100644
index 1d28d35..0000000
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+++ /dev/null
@@ -1,636 +0,0 @@
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- clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
- clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
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diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
deleted file mode 100644
index 85b4205..0000000
--- a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
+++ /dev/null
@@ -1,48 +0,0 @@
-# This script is designed to generate fabric Verilog netlists
-# with a fixed device layout
-# It will only output netlists to be used by backend tools,
-# i.e., Synopsys ICC2, including
-# - Verilog netlists
-# - fabric hierarchy description for ICC2's hierarchical flow
-# - Timing/Design constraints
-#
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
-
-# Read OpenFPGA simulation settings
-read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
-
-# Annotate the OpenFPGA architecture to VPR data base
-# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
-
-# Build the module graph
-# - Enabled compression on routing architecture modules
-# - Enable pin duplication on grid modules
-build_fabric --compress_routing #--verbose
-
-# Write the fabric hierarchy of module graph to a file
-# This is used by hierarchical PnR flows
-write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1
-
-# Write the Verilog netlist for FPGA fabric
-# - Enable the use of explicit port mapping in Verilog netlist
-# which is required by Synopsys ICC2 parser
-write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \
- --explicit_port_mapping \
- --verbose
-
-# Write the SDC files for PnR backend
-# - Turn on every options here
-write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
-
-# Write SDC to disable timing for configure ports
-write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
-
-# Finish and exit OpenFPGA
-exit
-
-# Note :
-# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
deleted file mode 100644
index b89d62c..0000000
--- a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
+++ /dev/null
@@ -1,37 +0,0 @@
-# This script is designed to generate fabric Verilog netlists
-# with a fixed device layout
-# It will only output netlists to be used by backend tools,
-# i.e., Synopsys ICC2, including
-# - Verilog netlists
-# - fabric hierarchy description for ICC2's hierarchical flow
-# - Timing/Design constraints
-#
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
-
-# Read OpenFPGA simulation settings
-read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
-
-# Annotate the OpenFPGA architecture to VPR data base
-# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
-
-# Build the module graph
-# - Enabled compression on routing architecture modules
-# - Enable pin duplication on grid modules
-build_fabric --compress_routing #--verbose
-
-# Write the SDC files for PnR backend
-# - Turn on every options here
-write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
-
-# Write SDC to disable timing for configure ports
-write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
-
-# Finish and exit OpenFPGA
-exit
-
-# Note :
-# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
deleted file mode 100644
index f2e45ea..0000000
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+++ /dev/null
@@ -1,71 +0,0 @@
-# This script is designed to generate Verilog testbenches
-# with a fixed device layout
-# It will only output netlists to be used by verification tools
-# including
-# - Verilog testbenches, used by ModelSim
-# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
-#
-#--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
-
-# Read OpenFPGA simulation settings
-read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
-
-# Annotate the OpenFPGA architecture to VPR data base
-# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup
-
-# Build the module graph
-# - Enabled compression on routing architecture modules
-# - Enable pin duplication on grid modules
-build_fabric --compress_routing #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream
-# - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --write_file arch_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write fabric-dependent bitstream
-write_fabric_bitstream --file fabric_bitstream.xml --format xml
-
-# Write the Verilog testbench for FPGA fabric
-# - We suggest the use of same output directory as fabric Verilog netlists
-# - Must specify the reference benchmark file if you want to output any testbenches
-# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
- --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
- --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
- --print_top_testbench \
- --print_preconfig_top_testbench \
- --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
- --explicit_port_mapping
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
-
-# Finish and exit OpenFPGA
-exit
-
-# Note :
-# To run verification at the end of the flow maintain source in ./SRC directory