diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml index 82c1658..fc8e81d 100644 --- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -22,5 +22,5 @@ LUT3_DELAY: 2.31e-9 LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 LUT4_DELAY: 2.6e-9 LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 -REGIN_TO_FF0_DELAY: 1.12e-9 +REGIN_TO_FF0_DELAY: 0.58e-9 FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/DOC/requirements.txt b/DOC/requirements.txt index 314f232..c3e7e66 100644 --- a/DOC/requirements.txt +++ b/DOC/requirements.txt @@ -9,6 +9,12 @@ sphinxcontrib-bibtex<2.0.0 sphinxcontrib-tikz +# Package required to embed youtube video +sphinxcontrib-yt + +# Package required to convert SVG for latex building +sphinxcontrib-svg2pdfconverter + #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1 #See: # * https://github.com/sphinx-doc/sphinx/issues/3951 diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg new file mode 100644 index 0000000..8b7cb01 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg @@ -0,0 +1,397 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 + + schematic_timing + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst index b736ea8..bbaf130 100644 --- a/DOC/source/datasheet/qlsofa_hd/index.rst +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -14,3 +14,5 @@ QLSOFA HD qlsofa_hd_clb_arch qlsofa_hd_circuit_design + + qlsofa_hd_timing diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index c05e1c7..8c204ed 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -46,6 +46,32 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ +.. _qlsofa_hd_fpga_arch_routing_arch: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The routing architecture shares the same principle as the SOFA HD routing architecture (See details in :ref:`sofa_hd_fpga_arch_routing_arch`). + +.. note:: Different from SOFA HD, each routing channel consists of 60 routing tracks. See details in :numref:`table_qlsofa_hd_fpga_arch_routing_track_distribution`. + +.. _table_qlsofa_hd_fpga_arch_routing_track_distribution: + +.. table:: Routing track distribution of QLSOFA HD FPGA + + +------------+------------------------------+ + | Track type | Number of tracks per channel | + +============+==============================+ + | Length-1 | 6 (10%) | + +------------+------------------------------+ + | Length-2 | 6 (10%) | + +------------+------------------------------+ + | Length-4 | 48 (80%) | + +------------+------------------------------+ + | Total | 60 | + +------------+------------------------------+ + + .. _qlsofa_hd_fpga_arch_scan_chain: Scan-chain diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst new file mode 100644 index 0000000..c5cfbf4 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst @@ -0,0 +1,100 @@ +.. _qlsofa_hd_timing: + +Timing Annotation +----------------- + +.. _qlsofa_hd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. + +.. _fig_qlsofa_hd_fle_arch_timing: + +.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in QLSOFA HD FPGA + + Schematic of a logic element used in QLSOFA HD FPGA + +.. _table_qlsofa_hd_fle_arch_timing: + +.. table:: Path delays of logic element in the QLSOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _qlsofa_hd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays of I/O blocks in QLSOFA HD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. + +.. _qlsofa_hd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_qlsofa_hd_routing_arch_timing`. + +.. _table_qlsofa_hd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the QLSOFA HD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.44 | + +---------------------------+------------------------------+ + | A -> C | 1.44 | + +---------------------------+------------------------------+ + | A -> D | 1.44 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg new file mode 100644 index 0000000..8b7cb01 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg @@ -0,0 +1,397 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 + + schematic_timing + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/sofa_chd/index.rst b/DOC/source/datasheet/sofa_chd/index.rst index a35e5fe..6a29d92 100644 --- a/DOC/source/datasheet/sofa_chd/index.rst +++ b/DOC/source/datasheet/sofa_chd/index.rst @@ -14,3 +14,5 @@ SOFA CHD sofa_chd_clb_arch sofa_chd_circuit_design + + sofa_chd_timing diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst new file mode 100644 index 0000000..65fef7a --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst @@ -0,0 +1,100 @@ +.. _sofa_chd_timing: + +Timing Annotation +----------------- + +.. _sofa_chd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`. + +.. _fig_sofa_chd_fle_arch_timing: + +.. figure:: ./figures/sofa_chd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in SOFA CHD FPGA + + Schematic of a logic element used in SOFA CHD FPGA + +.. _table_sofa_chd_fle_arch_timing: + +.. table:: Path delays of logic element in the SOFA CHD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _sofa_chd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`. + +.. _sofa_chd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`. + +.. _table_sofa_chd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the SOFA CHD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.44 | + +---------------------------+------------------------------+ + | A -> C | 1.44 | + +---------------------------+------------------------------+ + | A -> D | 1.44 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg new file mode 100644 index 0000000..78d1013 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_timing.svg @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-02 20:32:49 +0000 + + frac_lut4_timing_points + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + [0] + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + [1] + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + A + + + + + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg new file mode 100644 index 0000000..c8464f2 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_routing_arch.svg @@ -0,0 +1,365 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.4\n2021-04-03 00:25:42 +0000 + + Canvas 1 + + Layer 1 + + + + + + + + + + + Input Pin + + + + + Output Pin + + + + + + + + + + + + + SB MUX + + + + + CB MUX + + + + + Track + + + + + + + + + + CLB + [2][1] + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [1][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CLB + [3][1] + + + + + + + + + + + + + + + + + + + + + CLB + [4][1] + + + + + + + + + + + + + + + + + + CLB + [5][1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L4 Wire + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L2 Wire + + + + + L1 Wire + + + + + A + + + + + B + + + + + + + + + C + + + + + D + + + + + E + + + + + diff --git a/DOC/source/datasheet/sofa_hd/index.rst b/DOC/source/datasheet/sofa_hd/index.rst index 8bff100..3b82f44 100644 --- a/DOC/source/datasheet/sofa_hd/index.rst +++ b/DOC/source/datasheet/sofa_hd/index.rst @@ -14,3 +14,5 @@ SOFA HD sofa_hd_clb_arch sofa_hd_circuit_design + + sofa_hd_timing diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst index 5f503c9..9854a4a 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst @@ -59,6 +59,47 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ +.. _sofa_hd_fpga_arch_routing_arch: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers. +:numref:`fig_sofa_hd_routing_arch` illustrates the detailed organization of the routing architecture. + +.. _fig_sofa_hd_routing_arch: + +.. figure:: ./figures/sofa_hd_routing_arch.svg + :width: 80% + :alt: Detailed routing architecture + + Detailed routing architecture + +The routing architecture consists the following type of routing tracks: + +- Length-1 wires (``L1 wires``), which hop over 1 logic block (including I/O block) +- Length-2 wires (``L2 wires``), which hop over 2 logic block (including I/O block) +- Length-4 wires (``L4 wires``), which hop over 4 logic block (including I/O block) + +Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles. +Each routing channel consists of 40 routing tracks. See details in :numref:`table_sofa_hd_fpga_arch_routing_track_distribution`. + +.. _table_sofa_hd_fpga_arch_routing_track_distribution: + +.. table:: Routing track distribution of SOFA HD FPGA + + +------------+------------------------------+ + | Track type | Number of tracks per channel | + +============+==============================+ + | Length-1 | 4 (10%) | + +------------+------------------------------+ + | Length-2 | 4 (10%) | + +------------+------------------------------+ + | Length-4 | 32 (80%) | + +------------+------------------------------+ + | Total | 40 | + +------------+------------------------------+ + .. _sofa_hd_fpga_arch_scan_chain: Scan-chain diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst new file mode 100644 index 0000000..731eb72 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst @@ -0,0 +1,112 @@ +.. _sofa_hd_timing: + +Timing Annotation +----------------- + +.. _sofa_hd_timing_clb: + +Configurable Logic Block +^^^^^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. + +.. _fig_sofa_hd_fle_arch_timing: + +.. figure:: ./figures/sofa_hd_fle_arch_timing.svg + :scale: 30% + :alt: Schematic of a logic element used in SOFA HD FPGA + + Schematic of a logic element used in SOFA HD FPGA + +.. _table_sofa_hd_fle_arch_timing: + +.. table:: Path delays of logic element in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | in0 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[0] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in1 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in2 -> LUT3_out[1] [1]_ | 2.31 | + +-------------------------+------------------------------+ + | in0 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in1 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in2 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out [1]_ | 2.60 | + +-------------------------+------------------------------+ + | LUT3_out[0] -> A | 0.56 | + +-------------------------+------------------------------+ + | LUT4_out[0] -> A | 0.58 | + +-------------------------+------------------------------+ + | A -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | A -> FF[0] | 0.56 | + +-------------------------+------------------------------+ + | FF[0] -> out[0] | 0.88 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | LUT3_out[1] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + | FF[1] -> out[1] | 0.89 | + +-------------------------+------------------------------+ + | regin -> FF[0] | 0.58 | + +-------------------------+------------------------------+ + | FF[0] -> FF[1] | 0.56 | + +-------------------------+------------------------------+ + +.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. + +.. _sofa_hd_timing_io: + +I/O Block +^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`. + +.. _table_sofa_hd_io_timing: + +.. table:: Path delays of I/O circuit in the SOFA HD FPGA + + +-------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +=========================+==============================+ + | SOC_IN -> FPGA_IN | 0.11 | + +-------------------------+------------------------------+ + | FPGA_OUT -> SOC_OUT | 0.11 | + +-------------------------+------------------------------+ + +.. _sofa_hd_timing_routing: + +Routing Architecture +^^^^^^^^^^^^^^^^^^^^ + +The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`. + +.. _table_sofa_hd_routing_arch_timing: + +.. table:: Path delays of routing blocks in the SOFA HD FPGA + + +---------------------------+------------------------------+ + | Path / Delay | TT (unit: ns) | + +===========================+==============================+ + | A -> B | 1.61 | + +---------------------------+------------------------------+ + | A -> C | 1.61 | + +---------------------------+------------------------------+ + | A -> D | 1.61 | + +---------------------------+------------------------------+ + | B -> E | 1.38 | + +---------------------------+------------------------------+ + diff --git a/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png new file mode 100644 index 0000000..61d666f Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png differ diff --git a/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png new file mode 100644 index 0000000..a8672b5 Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/sofa_chd_layout.png differ diff --git a/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png b/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png new file mode 100644 index 0000000..579c431 Binary files /dev/null and b/DOC/source/device/hd_fpga/figures/sofa_hd_layout.png differ diff --git a/DOC/source/device/hd_fpga/hd_device_gallery.rst b/DOC/source/device/hd_fpga/hd_device_gallery.rst new file mode 100644 index 0000000..fc5e43d --- /dev/null +++ b/DOC/source/device/hd_fpga/hd_device_gallery.rst @@ -0,0 +1,39 @@ +.. _hd_fpga_device_gallery: + +Chip Gallery +------------ + +Here lists the images of each HD FPGA chips + +SOFA HD +^^^^^^^ + +SOFA HD is the base design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/sofa_hd_layout.png + :scale: 100% + :alt: Layout view of SOFA HD device in Caravel SoC + + Layout view of SOFA HD device in Caravel SoC + +QLSOFA HD +^^^^^^^^^ + +QLSOFA HD is the arithmetic-enhanced design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/qlsofa_hd_layout.png + :scale: 100% + :alt: Layout view of QLSOFA HD device in Caravel SoC + + Layout view of QLSOFA HD device in Caravel SoC + +SOFA CHD +^^^^^^^^ + +SOFA CHD is the performance-optimized design of the SOFA high-density eFPGA IPs + +.. figure:: ./figures/sofa_chd_layout.png + :scale: 100% + :alt: Layout view of SOFA CHD device in Caravel SoC + + Layout view of SOFA CHD device in Caravel SoC diff --git a/DOC/source/device/hd_fpga/index.rst b/DOC/source/device/hd_fpga/index.rst index a6802e3..dc6f0d1 100644 --- a/DOC/source/device/hd_fpga/index.rst +++ b/DOC/source/device/hd_fpga/index.rst @@ -10,3 +10,5 @@ HD FPGAs hd_device_comp hd_device_dcac + + hd_device_gallery diff --git a/DOC/source/device/introduction.rst b/DOC/source/device/introduction.rst index 8c43329..6bda114 100644 --- a/DOC/source/device/introduction.rst +++ b/DOC/source/device/introduction.rst @@ -17,4 +17,3 @@ We aims to empower embedded applications with its low-cost design approach but h :alt: 24-hour FPGA IP development: from PDK to production-ready layout 24-hour FPGA IP development: from PDK to production-ready layout - diff --git a/README.md b/README.md index b7e40f0..5640f1c 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,20 @@ ## Introduction -SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework +SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework. + +This repository provide the following support for the eFPGA IPs +- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA). +- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs. +- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications +- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs +- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details + +

+ + + +

## Quick Start @@ -22,6 +35,11 @@ python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY} Otherwise, you should provide full path using the option _--openfpga\_root\_path_ + +## Chip Gallery + +You can find a chip gallery in the online documentation. + ## Directory Organization * Keep this folder clean and organized as follows