diff --git a/DOC/source/arch/clb_arch.rst b/DOC/source/arch/clb_arch.rst
index 415fc26..ae830d9 100644
--- a/DOC/source/arch/clb_arch.rst
+++ b/DOC/source/arch/clb_arch.rst
@@ -25,6 +25,9 @@ Feedback connections between LEs are implemented by the global routing architect
 Multi-mode Logic Element
 ~~~~~~~~~~~~~~~~~~~~~~~~
 
+Physical Implementation
+^^^^^^^^^^^^^^^^^^^^^^^
+
 As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
 
 - a fracturable 4-input Look-Up Table (LUT)
@@ -40,9 +43,63 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
 
 The LE can operate in different modes to map logic function efficiently
 
-- 4-input LUT and single FF
-- Dual 3-input LUTs and 2 FFs
-- 2-bit shift registers
+- 4-input LUT and single FF (see details in :ref:`clb_arch_le_single_lut4_mode`).
+- Dual 3-input LUTs and 2 FFs (see details in :ref:`clb_arch_le_dual_lut3_mode`).
+- 2-bit shift registers (see details in :ref:`clb_arch_le_shift_reg_mode`).
+
+
+.. _clb_arch_le_single_lut4_mode:
+
+Operating mode: LUT4 + FF
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
+As depicted in :numref:`fig_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
+
+The operating mode is designed to efficiently implement 4-input functions. 
+
+.. _fig_fle_arch_single_lut4_mode:
+
+.. figure:: ./figures/fle_arch_single_lut4_mode.svg
+  :scale: 30%
+  :alt: Logic element schematic
+
+  Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
+
+.. _clb_arch_le_dual_lut3_mode:
+
+Operating mode: Dual-LUT3
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
+As depicted in :numref:`fig_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
+
+The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3. 
+
+.. _fig_fle_arch_dual_lut3_mode:
+
+.. figure:: ./figures/fle_arch_dual_lut3_mode.svg
+  :scale: 30%
+  :alt: Logic element schematic
+
+  Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
+
+.. _clb_arch_le_shift_reg_mode:
+
+Operating mode: Shift-Register
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+As depicted in :numref:`fig_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
+
+The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs. 
+
+.. _fig_fle_arch_shift_reg_mode:
+
+.. figure:: ./figures/fle_arch_shift_reg_mode.svg
+  :scale: 30%
+  :alt: Logic element schematic
+
+  Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
 
 .. _clb_arch_scan_chain: