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[Testbench] Start build caravel scff test

This commit is contained in:
tangxifan 2020-12-16 11:43:02 -07:00
parent 682d15875b
commit b5fa0733a2
1 changed files with 1 additions and 1 deletions
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2
TESTBENCH/common/caravel_fpga_io_test_rtl_include_netlists.v → TESTBENCH/common/caravel_qlsofa_hd_scff_test_rtl_include_netlists.v
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@ -6,7 +6,7 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
// Include caravel gate-level netlists // Include caravel gate-level netlists
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_rtl_include_netlists.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v"
// Include testbench files // Include testbench files
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v" `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v"