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Fix parsing error in FPGA1212_QLSOFA arch file. 

I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
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WRansohoff 2021-02-05 11:36:29 -06:00 committed by GitHub
parent da52aa67eb
commit b4e3440972
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1 changed files with 2 additions and 2 deletions
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FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml
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@ -230,10 +230,10 @@
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name=="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>