From b2573bf2422c64781e1a200b9ef5acb7216e6379 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Nov 2020 18:24:29 -0700 Subject: [PATCH] [Doc] Update I/O resource documentation to synchronize the changes on wrapper --- .../figures/fpga_io_map_wishbone_mode.svg | 44 ++++------ DOC/source/arch/figures/fpga_io_switch.svg | 83 +++---------------- DOC/source/arch/io_resource.rst | 2 +- 3 files changed, 32 insertions(+), 97 deletions(-) diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg index 67f148a..79ab841 100644 --- a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg +++ b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg @@ -1,6 +1,6 @@ - + @@ -28,7 +28,7 @@ - Produced by OmniGraffle 7.18\n2020-11-19 03:30:43 +0000 + Produced by OmniGraffle 7.18\n2020-11-21 01:06:55 +0000 wishbone_mode @@ -150,23 +150,18 @@ - Caravel Wishbone rst_i - Caravel Wishbone ack_o - Caravel Wishbone cyc_i - Caravel Wishbone stb_i + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone ack_o + Caravel Wishbone cyc_i - - - - - - 1 bit - + + @@ -210,11 +205,12 @@ - Caravel Wishbone we_i - Caravel Wishbone adr_i[31:0] - Caravel Wishbone dat_i[31:0] - Caravel Wishbone dat_o[31:0] - Caravel Wishbone sel_i[3:0] + Caravel Wishbone stb_i + Caravel Wishbone we_i + Caravel Wishbone adr_i[31:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone dat_o[31:0] + Caravel Wishbone sel_i[3:0] @@ -223,7 +219,7 @@ - 69 bit + 70 bit @@ -233,19 +229,15 @@ - gpio[31] + gpio[30] - - - - - - 3 bit + + 4 bit diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/arch/figures/fpga_io_switch.svg index c47bc8a..273f7d5 100644 --- a/DOC/source/arch/figures/fpga_io_switch.svg +++ b/DOC/source/arch/figures/fpga_io_switch.svg @@ -1,6 +1,6 @@ - + @@ -32,25 +32,12 @@ - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-19 03:30:21 +0000 + Produced by OmniGraffle 7.18\n2020-11-21 01:05:14 +0000 switch base - - - CCFF_TAIL -> Caravel GPIO[35] @@ -283,16 +270,17 @@ - - Caravel Wishbone rst_i - Caravel Wishbone stb_i - Caravel Wishbone cyc_i - Caravel Wishbone we_i + + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone stb_i + Caravel Wishbone cyc_i + Caravel Wishbone we_i - - + + @@ -336,8 +324,8 @@ - - 105 bit + + 106 bit @@ -350,7 +338,7 @@ - + Caravel Wishbone sel_i[3:0] Caravel Wishbone dat_i[31:0] Caravel Wishbone adr_i[31:0] @@ -358,51 +346,6 @@ Caravel Wishbone dat_o[31:0] - - - - - - - Caravel - Wishbone - clk_i - - - - - CLK - - - - - Caravel - GPIO[36] - - - - - - - - - - - - - - - - - - - - - - - Clock Switch Circuitry - - diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst index bf73f87..4773ef0 100644 --- a/DOC/source/arch/io_resource.rst +++ b/DOC/source/arch/io_resource.rst @@ -39,7 +39,7 @@ Accelerator Mode When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. :numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. -.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected. +.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected. .. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.