diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/arch/figures/fpga_io_switch.svg index 273f7d5..3caaabf 100644 --- a/DOC/source/arch/figures/fpga_io_switch.svg +++ b/DOC/source/arch/figures/fpga_io_switch.svg @@ -33,10 +33,10 @@ - Produced by OmniGraffle 7.18\n2020-11-21 01:05:14 +0000 - - switch - + Produced by OmniGraffle 7.18\n2020-11-29 03:10:55 +0000 + + v1.0 + base @@ -319,7 +319,7 @@ - IO_ISOL_N -> Caravel GPIO[1] + IO_ISOL_N <- Caravel GPIO[1] TEST_EN <- Caravel GPIO[0] diff --git a/HDL/common/README.md b/HDL/common/README.md new file mode 100644 index 0000000..01a748d --- /dev/null +++ b/HDL/common/README.md @@ -0,0 +1,10 @@ +# Skywater PDK +This directory contains the HDL netlists and code generator for FPGA fabrics. + +- **caravel_fpga_wrapper_hd.v**: The wrapper for FPGA fabric to interface the Caravel SoC, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. **This file is automatically generated by a Python script** +- **caravel_defines.v**: The parameters required for Caravel wrapper HDL codes +- **caravel_fpga_wrapper_hd_template.v**: The template HDL codes for the wrapper +- **digital_io_hd.v**: the I/O cell used by High-density FPGA, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. +- **sky130_fd_sc_hd_wrapper.v**: Wrapper codes for the standard cells from the Skywater 130nm Foundry High-Density Standard Cell Library +- **skywater_function_verification.v**: Include pre-processing flags to enable functional verification for FPGAs +- **wrapper_lines_generator.py**: Python script to generate the wrapper *caravel\_fpga\_wrapper\_hd.v* diff --git a/HDL/common/caravel_fpga_wrapper_hd.v b/HDL/common/caravel_fpga_wrapper_hd.v index 99d15e4..d237172 100644 --- a/HDL/common/caravel_fpga_wrapper_hd.v +++ b/HDL/common/caravel_fpga_wrapper_hd.v @@ -1,422 +1,3 @@ -/* - *------------------------------------------------------------- - * - * A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC - * - * The wrapper is a technology mapped netlist where the mode-switch - * multiplexers are mapped to the Skywater 130nm - * High-Density (HD) standard cells - * - *------------------------------------------------------------- - */ - -module fpga_top ( - // Fixed I/O interface from Caravel SoC definition - // DO NOT CHANGE!!! - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oen, - - // IOs - input [37:0] io_in, - output [37:0] io_out, - output [37:0] io_oeb -); - - // Modelsim does NOT like redefining wires that already in the - // input/output ports. The follow lines may be needed when - // `default_nettype none - // is enabled - //wire [`MPRJ_IO_PADS-1:0] io_in; - //wire [`MPRJ_IO_PADS-1:0] io_out; - //wire [`MPRJ_IO_PADS-1:0] io_oeb; - - // FPGA wires - wire prog_clk; - wire Test_en; - wire io_isol_n; - wire clk; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; - wire ccff_head; - wire ccff_tail; - wire sc_head; - wire sc_tail; - - // Switch between wishbone and logic analyzer - wire wb_la_switch; - wire wb_la_switch_b; - - // Inverted switch signal to drive tri-state buffers - // Use drive strength 8 as we will have 33 output pins which is driven by - // the buffers - sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b)); - - // Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24]; - assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]; - assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]; - - // Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15]; - assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9]; - assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9]; - - // Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13]; - assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11]; - assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11]; - - // Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface - assign ccff_head = io_in[12]; - assign io_out[12] = 1'b0; - assign io_oeb[12] = 1'b1; - - assign io_out[11] = sc_tail; - assign io_oeb[11] = 1'b0; - - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2]; - assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20]; - assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20]; - - assign io_isol_n = io_in[1]; - assign io_out[1] = 1'b0; - assign io_oeb[1] = 1'b1; - - assign Test_en = io_in[0]; - assign io_out[0] = 1'b0; - assign io_oeb[0] = 1'b1; - - // Wire-bond RIGHT, BOTTOM, LEFT side I/O of FPGA to BOTTOM-side of Caravel interface - // Autogenerate code start - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135])); - assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134])); - assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o)); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15])); - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132])); - assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131])); - assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130])); - assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129])); - assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128])); - assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127])); - assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126])); - assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125])); - assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124])); - assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123])); - assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122])); - assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121])); - assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120])); - assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119])); - assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118])); - assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117])); - assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116])); - assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115])); - assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114])); - assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113])); - assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112])); - assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111])); - assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110])); - assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109])); - assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108])); - assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107])); - assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106])); - assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105])); - assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104])); - assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103])); - assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102])); - assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101])); - assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100])); - assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99])); - assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98])); - assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97])); - assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96])); - assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95])); - assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94])); - assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93])); - assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92])); - assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91])); - assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90])); - assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89])); - assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88])); - assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87])); - assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86])); - assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85])); - assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84])); - assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83])); - assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82])); - assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81])); - assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80])); - assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79])); - assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78])); - assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77])); - assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76])); - assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75])); - assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74])); - assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73])); - assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72])); - assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71])); - assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70])); - assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69])); - assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68])); - assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67])); - assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66])); - assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65])); - assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64])); - assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63])); - assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63]; - sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62])); - assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118]; - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31])); - sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118])); - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119]; - assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120]; - assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121]; - assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122]; - assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123]; - assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124]; - assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125]; - assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126]; - assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22]; - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127]; - assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21]; - // Autogenerate code end - - // Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface - assign prog_clk = io_in[37]; - assign io_out[37] = 1'b0; - assign io_oeb[37] = 1'b1; - - // FPGA clock port can be driven by either wishbone clock or an GPIO - assign clk = io_in[36]; - assign io_out[36] = 1'b0; - assign io_oeb[36] = 1'b1; - - assign io_out[35] = ccff_tail; - assign io_oeb[35] = 1'b0; - - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27]; - assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143]; - assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143]; - - assign sc_head = io_in[26]; - assign io_out[26] = 1'b0; - assign io_oeb[26] = 1'b1; - - // I/O[25] is reserved for a switch between wishbone interface - // and logic analyzer - assign wb_la_switch = io_in[25]; - assign io_out[25] = 1'b0; - assign io_oeb[25] = 1'b1; - - // TODO: Connect spypad from FPGA to logic analyzer ports - - fpga_core fpga_core_uut(.prog_clk(prog_clk), - .Test_en(Test_en), - .clk(clk), - .IO_ISOL_N(io_isol_n), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), - .ccff_head(ccff_head), - .ccff_tail(ccff_tail), - .sc_head(sc_head), - .sc_tail(sc_tail) - ); - -endmodule +version https://git-lfs.github.com/spec/v1 +oid sha256:92abd3ec319ae191207d8b23efed64587c83e3e48c573e7ca4ba6407c65e73fb +size 37715 diff --git a/HDL/common/caravel_fpga_wrapper_hd_template.v b/HDL/common/caravel_fpga_wrapper_hd_template.v index a3395bb..448d320 100644 --- a/HDL/common/caravel_fpga_wrapper_hd_template.v +++ b/HDL/common/caravel_fpga_wrapper_hd_template.v @@ -1,159 +1,3 @@ -/* - *------------------------------------------------------------- - * - * A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC - * - * The wrapper is a technology mapped netlist where the mode-switch - * multiplexers are mapped to the Skywater 130nm - * High-Density (HD) standard cells - * - *------------------------------------------------------------- - */ - -module fpga_top ( - // Fixed I/O interface from Caravel SoC definition - // DO NOT CHANGE!!! - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oen, - - // IOs - input [37:0] io_in, - output [37:0] io_out, - output [37:0] io_oeb -); - - // Modelsim does NOT like redefining wires that already in the - // input/output ports. The follow lines may be needed when - // `default_nettype none - // is enabled - //wire [`MPRJ_IO_PADS-1:0] io_in; - //wire [`MPRJ_IO_PADS-1:0] io_out; - //wire [`MPRJ_IO_PADS-1:0] io_oeb; - - // FPGA wires - wire prog_clk; - wire Test_en; - wire io_isol_n; - wire clk; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; - wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; - wire ccff_head; - wire ccff_tail; - wire sc_head; - wire sc_tail; - - // Switch between wishbone and logic analyzer - wire wb_la_switch; - wire wb_la_switch_b; - - // Inverted switch signal to drive tri-state buffers - // Use drive strength 8 as we will have 33 output pins which is driven by - // the buffers - sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b)); - - // Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24]; - assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]; - assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]; - - // Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15]; - assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9]; - assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9]; - - // Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13]; - assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11]; - assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11]; - - // Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface - assign ccff_head = io_in[12]; - assign io_out[12] = 1'b0; - assign io_oeb[12] = 1'b1; - - assign io_out[11] = sc_tail; - assign io_oeb[11] = 1'b0; - - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2]; - assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20]; - assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20]; - - assign io_isol_n = io_in[1]; - assign io_out[1] = 1'b0; - assign io_oeb[1] = 1'b1; - - assign Test_en = io_in[0]; - assign io_out[0] = 1'b0; - assign io_oeb[0] = 1'b1; - - // Wire-bond RIGHT, BOTTOM, LEFT side I/O of FPGA to BOTTOM-side of Caravel interface - // Autogenerate code start - // Autogenerate code end - - // Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface - assign prog_clk = io_in[37]; - assign io_out[37] = 1'b0; - assign io_oeb[37] = 1'b1; - - // FPGA clock port can be driven by either wishbone clock or an GPIO - assign clk = io_in[36]; - assign io_out[36] = 1'b0; - assign io_oeb[36] = 1'b1; - - assign io_out[35] = ccff_tail; - assign io_oeb[35] = 1'b0; - - assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27]; - assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143]; - assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143]; - - assign sc_head = io_in[26]; - assign io_out[26] = 1'b0; - assign io_oeb[26] = 1'b1; - - // I/O[25] is reserved for a switch between wishbone interface - // and logic analyzer - assign wb_la_switch = io_in[25]; - assign io_out[25] = 1'b0; - assign io_oeb[25] = 1'b1; - - // TODO: Connect spypad from FPGA to logic analyzer ports - - fpga_core fpga_core_uut(.prog_clk(prog_clk), - .Test_en(Test_en), - .clk(clk), - .IO_ISOL_N(io_isol_n), - .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN), - .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT), - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR), - .ccff_head(ccff_head), - .ccff_tail(ccff_tail), - .sc_head(sc_head), - .sc_tail(sc_tail) - ); - -endmodule +version https://git-lfs.github.com/spec/v1 +oid sha256:0970910e47d809b8748958d5828b580dca8735205da533069af7ce6cb5a8ba34 +size 3246 diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.0.json b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json new file mode 100644 index 0000000..24be77f --- /dev/null +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.0.json @@ -0,0 +1,163 @@ +{ + "caravel_gpio_input_name": "io_in", + "caravel_gpio_output_name": "io_out", + "caravel_gpio_direction_name": "io_oeb", + "caravel_logic_analyzer_input_name": "la_data_in", + "caravel_logic_analyzer_output_name": "la_data_out", + "caravel_logic_analyzer_direction_name": "la_oen", + "caravel_wishbone_clock_input_name": "wbs_clk_i", + "caravel_wishbone_reset_input_name": "wbs_rst_i", + "caravel_wishbone_ack_output_name": "wbs_ack_o", + "caravel_wishbone_cyc_input_name": "wbs_cyc_i", + "caravel_wishbone_stb_input_name": "wbs_stb_i", + "caravel_wishbone_we_input_name": "wbs_we_i", + "caravel_wishbone_sel_input_name": "wbs_sel_i", + "caravel_wishbone_address_input_name": "wbs_adr_i", + "caravel_wishbone_data_input_name": "wbs_dat_i", + "caravel_wishbone_data_output_name": "wbs_dat_o", + "fpga_gpio_input_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "fpga_gpio_output_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT", + "fpga_gpio_direction_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "mode_switch_pin_name": "wb_la_switch", + "inverted_mode_switch_pin_name": "wb_la_switch_b", + "pins": [ + { + "fpga_pin_type": "io", + "fpga_pin_index": "0:11", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["24:13"] + }, + { + "fpga_pin_type": "ccff_head", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["12:12"] + }, + { + "fpga_pin_type": "sc_tail", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["output"], + "caravel_pin_index": ["11:11"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "12:20", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["10:2"] + }, + { + "fpga_pin_type": "io_isol_n", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["1:1"] + }, + { + "fpga_pin_type": "test_en", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "21:23", + "caravel_pin_type": ["logic_analyzer_io"], + "caravel_pin_index": ["127:125"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "24:29", + "caravel_pin_type": ["logic_analyzer_io"], + "caravel_pin_index": ["124:119"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "30:61", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_data_output"], + "caravel_pin_index": ["118:87", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "62:93", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_data_input"], + "caravel_pin_index": ["86:55", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "94:125", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_address_input"], + "caravel_pin_index": ["54:23", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "126:129", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_sel_input"], + "caravel_pin_index": ["22:19", "0:3"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "130:130", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_we_input"], + "caravel_pin_index": ["18:18", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "131:131", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_stb_input"], + "caravel_pin_index": ["17:17", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "132:132", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_cyc_input"], + "caravel_pin_index": ["16:16", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "133:133", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_ack_output"], + "caravel_pin_index": ["15:15", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "134:134", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_reset_input"], + "caravel_pin_index": ["14:14", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "135:135", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_clock_input"], + "caravel_pin_index": ["13:13", "0:0"] + }, + { + "fpga_pin_type": "prog_clk", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["37:37"] + }, + { + "fpga_pin_type": "clk", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["36:36"] + }, + { + "fpga_pin_type": "sc_tail", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["output"], + "caravel_pin_index": ["35:35"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "136:143", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["34:27"] + }, + { + "fpga_pin_type": "sc_head", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["26:26"] + } + ] +} diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json new file mode 100644 index 0000000..bec2e01 --- /dev/null +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -0,0 +1,175 @@ +{ + "caravel_gpio_input_name": "io_in", + "caravel_gpio_output_name": "io_out", + "caravel_gpio_direction_name": "io_oeb", + "caravel_logic_analyzer_input_name": "la_data_in", + "caravel_logic_analyzer_output_name": "la_data_out", + "caravel_logic_analyzer_direction_name": "la_oen", + "caravel_wishbone_clock_input_name": "wbs_clk_i", + "caravel_wishbone_reset_input_name": "wbs_rst_i", + "caravel_wishbone_ack_output_name": "wbs_ack_o", + "caravel_wishbone_cyc_input_name": "wbs_cyc_i", + "caravel_wishbone_stb_input_name": "wbs_stb_i", + "caravel_wishbone_we_input_name": "wbs_we_i", + "caravel_wishbone_sel_input_name": "wbs_sel_i", + "caravel_wishbone_address_input_name": "wbs_adr_i", + "caravel_wishbone_data_input_name": "wbs_dat_i", + "caravel_wishbone_data_output_name": "wbs_dat_o", + "fpga_gpio_input_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_IN", + "fpga_gpio_output_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT", + "fpga_gpio_direction_name": "gfpga_pad_EMBEDDED_IO_HD_SOC_DIR", + "mode_switch_pin_name": "wb_la_switch", + "inverted_mode_switch_pin_name": "wb_la_switch_b", + "pins": [ + { + "fpga_pin_type": "io", + "fpga_pin_index": "0:11", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["24:13"] + }, + { + "fpga_pin_type": "ccff_head", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["12:12"] + }, + { + "fpga_pin_type": "sc_tail", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["output"], + "caravel_pin_index": ["11:11"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "12:18", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["10:4"] + }, + { + "fpga_pin_type": "prog_reset", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["3:3"] + }, + { + "fpga_pin_type": "reset", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["2:2"] + }, + { + "fpga_pin_type": "io_isol_n", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["1:1"] + }, + { + "fpga_pin_type": "test_en", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "19:23", + "caravel_pin_type": ["logic_analyzer_io"], + "caravel_pin_index": ["127:123"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "24:29", + "caravel_pin_type": ["logic_analyzer_io"], + "caravel_pin_index": ["122:117"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "30:61", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_data_output"], + "caravel_pin_index": ["116:85", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "62:93", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_data_input"], + "caravel_pin_index": ["84:53", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "94:125", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_address_input"], + "caravel_pin_index": ["52:21", "0:31"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "126:129", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_sel_input"], + "caravel_pin_index": ["20:17", "0:3"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "130:130", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_we_input"], + "caravel_pin_index": ["16:16", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "131:131", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_stb_input"], + "caravel_pin_index": ["15:15", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "132:132", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_cyc_input"], + "caravel_pin_index": ["14:14", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "133:133", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_ack_output"], + "caravel_pin_index": ["13:13", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "134:134", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_reset_input"], + "caravel_pin_index": ["12:12", "0:0"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "135:135", + "caravel_pin_type": ["logic_analyzer_io", "wishbone_clock_input"], + "caravel_pin_index": ["11:11", "0:0"] + }, + { + "fpga_pin_type": "prog_clk", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["37:37"] + }, + { + "fpga_pin_type": "clk", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["36:36"] + }, + { + "fpga_pin_type": "sc_tail", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["output"], + "caravel_pin_index": ["35:35"] + }, + { + "fpga_pin_type": "io", + "fpga_pin_index": "136:143", + "caravel_pin_type": ["gpio"], + "caravel_pin_index": ["34:27"] + }, + { + "fpga_pin_type": "sc_head", + "fpga_pin_index": "0:0", + "caravel_pin_type": ["input"], + "caravel_pin_index": ["26:26"] + } + ] +} diff --git a/HDL/common/wrapper_lines_generator.py b/HDL/common/wrapper_lines_generator.py index 334b2c3..a4808f1 100644 --- a/HDL/common/wrapper_lines_generator.py +++ b/HDL/common/wrapper_lines_generator.py @@ -12,6 +12,7 @@ import shutil import re import argparse import logging +import json ##################################################################### # Initialize logger @@ -26,111 +27,214 @@ parser = argparse.ArgumentParser( description='Generator for technology-mapped wrapper') parser.add_argument('--template_netlist', default='caravel_fpga_wrapper_hd_template.v', help='Specify template verilog netlist') +parser.add_argument('--pin_assignment_file', required=True, + help='Specify the json file constaining pin assignment information') parser.add_argument('--output_verilog', default='caravel_fpga_wrapper_hd.v', help='Specify output verilog file path') args = parser.parse_args() ##################################################################### -# Define Wishbone interface pin sequence -# The list start from left-side of the wrapper to the right side -# Target FPGA gpio start from 135, 134 ... +# Check options: +# - Input json file must be valid +# Otherwise, error out ##################################################################### -wishbone_pins = ['wb_clk_i', 'wb_rst_i', - 'wbs_ack_o', 'wbs_cyc_i', - 'wbs_stb_i', 'wbs_we_i'] - -wishbone_pins.extend([f"wbs_sel_i[{i}]" for i in range(4)]) -wishbone_pins.extend([f"wbs_adr_i[{i}]" for i in range(32)]) -wishbone_pins.extend([f"wbs_dat_i[{i}]" for i in range(32)]) -wishbone_pins.extend([f"wbs_dat_o[{i}]" for i in range(32)]) +if not isfile(args.pin_assignment_file): + logging.error("Invalid pin assignment file: " + args.pin_assignment_file + "\nFile does not exist!\n") + exit(1) ##################################################################### -# Define Logic Analyzer interface pin sequence -# The list start from left-side of the wrapper to the right side -# Target FPGA gpio start from 135, 134 ... +# Parse the json file ##################################################################### -logic_analyzer_pins = [] -for ipin in range(13, 128): - logic_analyzer_pins.append(["la_data_in[" + str(ipin) + "]", - "la_data_out[" + str(ipin) + "]", "la_oen[" + str(ipin) + "]"]) +json_file = open(args.pin_assignment_file, "r") +pin_data = json.load(json_file) + +##################################################################### +# A function to parse pin range from json data +# JSON pin range format is LSB:MSB +# Return pin range format is [LSB, MSB] as a list +##################################################################### +def parse_json_pin_range(json_range) : + pin_range_str = json_range.split(':') + assert(2 == len(pin_range_str)) + # If the range is in decend order, we will decrease the MSB by 1 + if (int(pin_range_str[0]) > int(pin_range_str[1])) : + return range(int(pin_range_str[0]), int(pin_range_str[1]) - 1, -1) + # If the range is in acend order, we will increase the MSB by 1 + return range(int(pin_range_str[0]), int(pin_range_str[1]) + 1) ##################################################################### # Generate wrapper lines ##################################################################### netlist_lines = [] -num_wishbone_pins = len(wishbone_pins) -num_logic_analyzer_pins = len(logic_analyzer_pins) -num_gpio_pins = 135 - 21 + 1 -print("Number of Wishbone pins: " + str(num_wishbone_pins)) -print("Number of logic analyzer pins: " + str(num_logic_analyzer_pins)) -print("Number of gpio pins: " + str(num_gpio_pins)) +# Walk through the array containing the pin information +for pin_info in pin_data['pins']: + # Deposit a tab to respect the HDL coding indent + curr_line = "" + # TODO: Check codes that ensure the pin index should match + assert(0 < len(pin_info['caravel_pin_type'])) + assert(0 < len(pin_info['caravel_pin_index'])) + # + # Branch on the types of connnections: + # - FPGA I/O to Caravel GPIO + if (("io" == pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("gpio" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # Connect all the input, output and direction port + # FPGA input <- Caravel input + curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "];"; + netlist_lines.append(" " + curr_line + "\n") + # FPGA output -> Caravel output + curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = " \ + + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];"; + netlist_lines.append(" " + curr_line + "\n") + # FPGA direction -> Caravel direction + curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = " \ + + pin_data['fpga_gpio_direction_name'] + "[" + str(indices[0]) + "];"; + netlist_lines.append(" " + curr_line + "\n") -assert num_wishbone_pins < num_logic_analyzer_pins -assert num_logic_analyzer_pins == num_gpio_pins + # - FPGA control input ports to Caravel GPIO + if (("io" != pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("input" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # Connect the FPGA input port to the Caravel input + curr_line = "assign " + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "];"; + netlist_lines.append(" " + curr_line + "\n") + # Tie Caravel output port to logic '0' + curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = 1'b0;" + netlist_lines.append(" " + curr_line + "\n") + # Tie Caravel direction port to logic '1' + curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = 1'b1;" + netlist_lines.append(" " + curr_line + "\n") -for ipin in range(0, num_gpio_pins): - curr_line = "" - if ((ipin < num_wishbone_pins) and (ipin < num_logic_analyzer_pins)): - # If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX - # otherwise, this is an output pin, we just wire the input to logic analyzer - if ((wishbone_pins[ipin].endswith("_i")) or (re.search(r'_i\[\d+\]$', wishbone_pins[ipin], re.M | re.I))): - ############################################################## - # SOC INPUT will be directly driven by either - # - the Wishbone input - # or - # - the logic analyzer input - # through a multiplexer controlled by the signal 'wb_la_switch - curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(wb_la_switch), .A1(" + str( - wishbone_pins[ipin]) + "), .A0(" + str(logic_analyzer_pins[ipin][0]) + "), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(135 - ipin) + "]));" - netlist_lines.append(curr_line + "\n") - ############################################################## - # SOC OUTPUT will drive an output of logic analyzer - # since this I/O is going to interface a Wishbone input only - curr_line = " " + "assign " + \ - str(logic_analyzer_pins[ipin][1]) + \ - " = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];" - netlist_lines.append(curr_line + "\n") - elif ((wishbone_pins[ipin].endswith("_o")) or (re.search(r'_o\[\d+\]$', wishbone_pins[ipin], re.M | re.I))): - ############################################################## - # SOC INPUT will be directly driven by logic analyzer - # since this I/O is going to interface a Wishbone output only - curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str( - 135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";" - netlist_lines.append(curr_line + "\n") - ############################################################## - # SOC OUTPUT will drive the Wishbone output through a tri-state buffer - # As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch' - curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_WB (" + \ - ".TE_B(wb_la_switch_b), " + \ - ".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \ - ".Z(" + str(wishbone_pins[ipin]) + ")" + \ - ");" - netlist_lines.append(curr_line + "\n") - ############################################################## - # SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer - # As the buffer is enabled by logic '0', we use the 'wb_la_switch' - curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_LA (" + \ - ".TE_B(wb_la_switch), " + \ - ".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \ - ".Z(" + str(logic_analyzer_pins[ipin][1]) + ")" + \ - ");" - netlist_lines.append(curr_line + "\n") + # - FPGA control output ports to Caravel GPIO + if (("io" != pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("output" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + # Bypass the Caravel input + # Connect Caravel output port to FPGA control output + curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = " \ + + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "];"; + netlist_lines.append(" " + curr_line + "\n") + # Tie Caravel direction port to logic '0' + curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = 1'b0;" + netlist_lines.append(" " + curr_line + "\n") - elif ((ipin >= num_wishbone_pins) and (ipin < num_logic_analyzer_pins)): + # - FPGA I/O ports to Caravel logic analyzer I/O only + if (("io" == pin_info['fpga_pin_type']) \ + and (1 == len(pin_info['caravel_pin_type'])) \ + and ("logic_analyzer_io" == pin_info['caravel_pin_type'][0])): + # Should have only 1 port in caravel + assert(1 == len(pin_info['caravel_pin_type'])) + assert(1 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + caravel_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range))) + for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : + ############################################################## + # SOC INPUT will be directly driven by logic analyzer + # since this I/O is going to interface logic analyzer input only + curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "]" + ";" + netlist_lines.append(" " + curr_line + "\n") + ############################################################## + # SOC OUTPUT will directly drive logic analyzer + # since this I/O is going to interface logic analyzer output only + curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "]" \ + + " = " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];" + netlist_lines.append(" " + curr_line + "\n") + + # - FPGA I/O ports to Caravel logic analyzer I/O and Wishbone interface + if (("io" == pin_info['fpga_pin_type']) \ + and (2 == len(pin_info['caravel_pin_type'])) \ + and ("logic_analyzer_io" == pin_info['caravel_pin_type'][0]) \ + and (pin_info['caravel_pin_type'][1].startswith("wishbone"))): + # Should have only 2 port in caravel + assert(2 == len(pin_info['caravel_pin_type'])) + assert(2 == len(pin_info['caravel_pin_index'])) + # Get pin range + fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index']) + la_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][0]) + wb_io_pin_range = parse_json_pin_range(pin_info['caravel_pin_index'][1]) + assert(len(list(fpga_io_pin_range)) == len(list(la_io_pin_range))) + assert(len(list(fpga_io_pin_range)) == len(list(wb_io_pin_range))) + + # If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX + # otherwise, this is an output pin, we just wire the input to logic analyzer + if (pin_info['caravel_pin_type'][1].endswith("_input")): + for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_io_pin_range)) : + ############################################################## + # SOC INPUT will be directly driven by either + # - the Wishbone input + # or + # - the logic analyzer input + # through a multiplexer controlled by the signal 'wb_la_switch + curr_line = "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(indices[0]) + "_MUX (" \ + + ".S(" + pin_data['mode_switch_pin_name'] + "), " \ + + ".A1(" + pin_data['caravel_' + pin_info['caravel_pin_type'][1] + '_name'] + "[" + str(indices[2]) + "]), " \ + + ".A0(" + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "]), " \ + + ".X(" + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "])" \ + + ");" + netlist_lines.append(" " + curr_line + "\n") + ############################################################## + # SOC OUTPUT will drive an output of logic analyzer + # since this I/O is going to interface a Wishbone input only + curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "]" \ + + " = " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];" + netlist_lines.append(" " + curr_line + "\n") + elif (pin_info['caravel_pin_type'][1].endswith("_output")): + for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_io_pin_range)) : ############################################################## # SOC INPUT will be directly driven by logic analyzer - # since this I/O is going to interface logic analyzer input only - curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str( - 135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";" - netlist_lines.append(curr_line + "\n") + # since this I/O is going to interface a Wishbone output only + curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \ + + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "];" + netlist_lines.append(" " + curr_line + "\n") ############################################################## - # SOC OUTPUT will directly drive logic analyzer - # since this I/O is going to interface logic analyzer output only - curr_line = " " + "assign " + \ - str(logic_analyzer_pins[ipin][1]) + \ - " = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];" - netlist_lines.append(curr_line + "\n") + # SOC OUTPUT will drive the Wishbone output through a tri-state buffer + # As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch' + curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(indices[0]) + "_DEMUX_WB (" \ + + ".TE_B(" + pin_data['inverted_mode_switch_pin_name'] + "), " \ + + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]), " \ + + ".Z(" + pin_data['caravel_' + pin_info['caravel_pin_type'][1] + '_name'] + "[" + str(indices[2]) + "])" \ + + ");" + netlist_lines.append(" " + curr_line + "\n") + ############################################################## + # SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer + # As the buffer is enabled by logic '0', we use the 'wb_la_switch' + curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(indices[0]) + "_DEMUX_LA (" \ + + ".TE_B(" + pin_data['mode_switch_pin_name'] + "), " \ + + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]), " \ + + ".Z(" + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "])" \ + + ");" + netlist_lines.append(" " + curr_line + "\n") if isfile(args.output_verilog): os.remove(args.output_verilog) diff --git a/MSIM/common/run_post_pnr_msim_task.py b/MSIM/common/run_post_pnr_msim_task.py index 10cb27e..09b538e 100644 --- a/MSIM/common/run_post_pnr_msim_task.py +++ b/MSIM/common/run_post_pnr_msim_task.py @@ -49,7 +49,7 @@ logging.info("Found " + str(len(testbench_files)) + " testbenches") # Try to create the directory of Modelsim projects ##################################################################### parent_dir_abspath = dirname(dirname(abspath(__file__))) -msim_task_dir_abspath = abspath(parent_dir_abspath + args.task_name) + "/postpnr/verilog_testbench"; +msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/postpnr/verilog_testbench"; os.makedirs(msim_task_dir_abspath, exist_ok=True) #####################################################################