diff --git a/.github/workflows/quick_test.sh b/.github/workflows/quick_test.sh index aff8aec..6c3b403 100755 --- a/.github/workflows/quick_test.sh +++ b/.github/workflows/quick_test.sh @@ -9,9 +9,17 @@ set -e ############################################## # Initialize the repository # - Generate final version of architecture files -# - Run FPGA tasks to validate netlist generations +# - Run FPGA tasks to validate netlist generations python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA +# Post processing netlist to use custom cells +python3 HDL/common/custom_cell_mux_primitive_generator.py --template_netlist HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives.v --output_verilog HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives_hd.v + +############################################## +# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os +python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v +python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v + ############################################## # Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v @@ -20,7 +28,5 @@ python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/cara ############################################## # Generate post-PnR testbenches python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json -python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json -python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml index b427d66..6c7ef58 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml @@ -160,7 +160,11 @@ +<<<<<<< HEAD +======= + +>>>>>>> origin/master @@ -169,7 +173,11 @@ +<<<<<<< HEAD +======= + +>>>>>>> origin/master @@ -201,7 +209,7 @@ - + @@ -228,7 +236,7 @@ - + @@ -282,9 +290,9 @@ - - - + + + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 97989e2..06558f6 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -230,7 +230,7 @@ - + diff --git a/DOC/source/arch/index.rst b/DOC/source/arch/index.rst deleted file mode 100644 index d28ed8e..0000000 --- a/DOC/source/arch/index.rst +++ /dev/null @@ -1,11 +0,0 @@ -.. _arch: - Architecture - -.. toctree:: - :maxdepth: 2 - - fpga_arch - - io_resource - - clb_arch diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst deleted file mode 100644 index 4773ef0..0000000 --- a/DOC/source/arch/io_resource.rst +++ /dev/null @@ -1,107 +0,0 @@ -.. _io_resource: - -I/O Resources -------------- - -.. _io_resource_overview: - -Overview -~~~~~~~~ - -The *High-Density* (HD) FPGA IP has 144 I/O pins as shown in :numref:`fig_fpga_io_switch`. - -Among the 144 I/Os, - -- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs). - -- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details. - -.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components. - -.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. - -.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`. - -.. _fig_fpga_io_switch: - -.. figure:: ./figures/fpga_io_switch.svg - :scale: 20% - :alt: I/O arrangement of FPGA IP - - I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface - - -.. _io_resource_accelerator: - -Accelerator Mode -~~~~~~~~~~~~~~~~ - -When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. -:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. - -.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected. - -.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator. - -.. _fig_fpga_io_map_wishbone_mode: - -.. figure:: ./figures/fpga_io_map_wishbone_mode.svg - :scale: 20% - :alt: I/O arrangement of FPGA IP when interfacing wishbone bus - - I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus - -.. _io_resource_debug: - -Debug Mode -~~~~~~~~~~ - -When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. -:numref:`fig_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. - -.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose. - -.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows: - - - all the I/O directionality is set to **input mode**. - - all the output ports is pulled down to **logic ``0``**. - -.. _fig_fpga_io_map_logic_analyzer_mode: - -.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg - :scale: 20% - :alt: I/O arrangement of FPGA IP when interfacing logic analyzer - - I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer - -.. _io_resource_circuit: - -FPGA I/O Circuit -~~~~~~~~~~~~~~~~ - -As shown in :numref:`fig_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_fpga_arch`) is an digital I/O cell with - -- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. - - .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! - -- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid - - - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode - - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode - -- An internal configurable memory element to control the direction of I/O cell - -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where - -- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode - -- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode - -.. _fig_embedded_io_schematic: - -.. figure:: ./figures/embedded_io_schematic.svg - :scale: 30% - :alt: Schematic of embedded I/O cell used in FPGA - - Schematic of embedded I/O cell used in FPGA diff --git a/DOC/source/datasheet/index.rst b/DOC/source/datasheet/index.rst new file mode 100644 index 0000000..ef6404f --- /dev/null +++ b/DOC/source/datasheet/index.rst @@ -0,0 +1,9 @@ +.. _datasheet: + Datasheets + +.. toctree:: + :maxdepth: 2 + + sofa_hd/index + + qlsofa_hd/index diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_clb_arch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_clb_arch.svg new file mode 100644 index 0000000..bbda53b --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_clb_arch.svg @@ -0,0 +1,751 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 18:25:52 +0000 + + qlsofa_hd + + le + + + + + + + CLB + + + + + ... + + + + + reg_in + + + + + sc_in + + + + + reg_out + + + + + sc_out + + + + + I0[0] + + + + + I0[1] + + + + + I0[2] + + + + + I0i[0] + + + + + CLK + + + + + Test_en + + + + + I1[0] + + + + + I1[1] + + + + + I1[2] + + + + + I1i[0] + + + + + I7[0] + + + + + I7[1] + + + + + I7[2] + + + + + I7i[0] + + + + + O[0] + + + + + O[1] + + + + + O[2] + + + + + O[3] + + + + + O[14] + + + + + O[15] + + + + + cin + + + + + cout + + + + + + + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [0] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + cin + + + + + cout + + + + + Reset + + + + + + + + + + + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [1] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + cin + + + + + cout + + + + + Reset + + + + + + + + + + + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [7] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + cin + + + + + cout + + + + + Reset + + + + + + + + + Reset + + + + + wire + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOC/source/arch/figures/embedded_io_schematic.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg similarity index 100% rename from DOC/source/arch/figures/embedded_io_schematic.svg rename to DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg diff --git a/DOC/source/arch/figures/fabric_scan_chain.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg similarity index 100% rename from DOC/source/arch/figures/fabric_scan_chain.svg rename to DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg new file mode 100644 index 0000000..a559eef --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 16:24:40 +0000 + + dual_lut3 + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_schematic.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_schematic.svg new file mode 100644 index 0000000..064d224 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_schematic.svg @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 16:24:40 +0000 + + schematic + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_shift_register_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_shift_register_mode.svg new file mode 100644 index 0000000..c239b7e --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_shift_register_mode.svg @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 16:24:40 +0000 + + shift_register + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_single_lut4_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_single_lut4_mode.svg new file mode 100644 index 0000000..018c66d --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_single_lut4_mode.svg @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 16:24:40 +0000 + + single_lut4 + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_soft_adder_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_soft_adder_mode.svg new file mode 100644 index 0000000..35ffba6 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_soft_adder_mode.svg @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-04 16:24:40 +0000 + + soft_adder + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + Reset + + + + + + + + + + + + diff --git a/DOC/source/arch/figures/fpga_arch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg similarity index 100% rename from DOC/source/arch/figures/fpga_arch.svg rename to DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg new file mode 100644 index 0000000..e29fd87 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg @@ -0,0 +1,247 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-29 00:20:31 +0000 + + v1.1 + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[18] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 7 bit + + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 5 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[123:127] + + + + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + … + + + + + + + + + Caravel Logic Analyzer + la_data_in/out/oen[15:122] + + + + + + + + + 108 bit + + + + + + + + 4 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[11:14] + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg new file mode 100644 index 0000000..4744bdb --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg @@ -0,0 +1,259 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-29 00:23:07 +0000 + + v1.1 + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[18] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 7 bit + + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone ack_o + Caravel Wishbone cyc_i + + + + + + + + + + + + + + + + + 32 bit + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + Caravel Wishbone stb_i + Caravel Wishbone we_i + Caravel Wishbone adr_i[31:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone dat_o[31:0] + Caravel Wishbone sel_i[3:0] + + + + + + + + + 70 bit + + + + + … + + + + + gpio[30] + + + + + + + + 3 bit + + + + + + + + + 1 bit + + + + + … + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg new file mode 100644 index 0000000..3e91b9b --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg @@ -0,0 +1,353 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-29 03:10:55 +0000 + + v1.1 + + base + + + CCFF_TAIL -> Caravel GPIO[35] + CLK <- Caravel GPIO[36] + PROG_CLK <- Caravel GPIO[37] + + + + + + + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[18] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 7 bit + + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 5 bit + + + + + + + + 4 bit + + + + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + … + + + + + Caravel Logic Analyzer + la_data_in/out/oen[11:127] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel + GPIO[25] + + + + + + + + + + + + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone stb_i + Caravel Wishbone cyc_i + Caravel Wishbone we_i + + + + + + + + + Mode switch truth table: + - When Caravel GPIO[25] is logic ‘1’, FPGA is interfacing the Wishbone bus + - When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer + + + + + + + + + CCFF_HEAD <- Caravel GPIO[12] + SC_TAIL -> Caravel GPIO[11] + + + + + + SC_HEAD <- Caravel GPIO[26] + + + + + + + + + + + + + + + + + PROG_RESET <- Caravel GPIO[3] + RESET <- Caravel GPIO[2] + IO_ISOL_N <- Caravel GPIO[1] + TEST_EN <- Caravel GPIO[0] + + + + + 106 bit + + + + + 117 bit + + + + + + + + + Caravel Wishbone sel_i[3:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone adr_i[31:0] + Caravel Wishbone ack_o + Caravel Wishbone dat_o[31:0] + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst new file mode 100644 index 0000000..09e8665 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -0,0 +1,16 @@ +.. _datasheet_sofa_hd: + QLSOFA HD + +QLSOFA HD +--------- + +.. toctree:: + :maxdepth: 2 + + qlsofa_hd_fpga_arch + + qlsofa_hd_io_resource + + qlsofa_hd_clb_arch + + qlsofa_hd_circuit_design diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst new file mode 100644 index 0000000..90d527b --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst @@ -0,0 +1,36 @@ +.. _qlsofa_hd_circuit_design: + +Circuit Designs +--------------- + +.. _qlsofa_hd_circuit_design_io: + +I/O Circuit +^^^^^^^^^^^ + +As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with + +- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. + + .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! + +- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid + + - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode + - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode + +- An internal configurable memory element to control the direction of I/O cell + +The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where + +- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode + +- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode + +.. _fig_qlsofa_hd_embedded_io_schematic: + +.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg + :scale: 30% + :alt: Schematic of embedded I/O cell used in FPGA + + Schematic of embedded I/O cell used in FPGA diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_clb_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_clb_arch.rst new file mode 100644 index 0000000..446a0a0 --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_clb_arch.rst @@ -0,0 +1,131 @@ +.. _qlsofa_hd_clb_arch: + +Configurable Logic Block +------------------------ + +.. _qlsofa_hd_clb_arch_generality: + +Generality +~~~~~~~~~~ + +Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_qlsofa_hd_clb_arch`. +All the pins of the LEs are directly wired to CLB pins without a local routing architecture. +Feedback connections between LEs are implemented by the global routing architecture outside the CLBs. + +.. _fig_qlsofa_hd_clb_arch: + +.. figure:: ./figures/qlsofa_hd_clb_arch.svg + :scale: 20% + :alt: Configurable Logic Block schematic + + Configurable logic block schematic + +.. _qlsofa_hd_clb_arch_le: + +Multi-mode Logic Element +~~~~~~~~~~~~~~~~~~~~~~~~ + +Physical Implementation +^^^^^^^^^^^^^^^^^^^^^^^ + +As shown in :numref:`fig_qlsofa_hd_fle_arch_schematic`, each Logic Element (LE) consists of + +- a fracturable 4-input Look-Up Table (LUT) +- two D-type Flip-Flops (FF) + +.. _fig_qlsofa_hd_fle_arch_schematic: + +.. figure:: ./figures/qlsofa_hd_fle_arch_schematic.svg + :scale: 30% + :alt: Logic element schematic + + Detailed schematic of a logic element + +The LE can operate in different modes to map logic function efficiently + +- 4-input LUT and single FF (see details in :ref:`qlsofa_hd_clb_arch_le_single_lut4_mode`). +- Dual 3-input LUTs and 2 FFs (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`). +- 2-bit shift registers (see details in :ref:`qlsofa_hd_clb_arch_le_shift_reg_mode`). + + +.. _qlsofa_hd_clb_arch_le_single_lut4_mode: + +Operating mode: LUT4 + FF +^^^^^^^^^^^^^^^^^^^^^^^^^ + +The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements. +As depicted in :numref:`fig_qlsofa_hd_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic. + +The operating mode is designed to efficiently implement 4-input functions. + +.. _fig_qlsofa_hd_fle_arch_single_lut4_mode: + +.. figure:: ./figures/qlsofa_hd_fle_arch_single_lut4_mode.svg + :scale: 30% + :alt: Logic element schematic + + Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources). + +.. _qlsofa_hd_clb_arch_le_dual_lut3_mode: + +Operating mode: Dual-LUT3 +^^^^^^^^^^^^^^^^^^^^^^^^^ + +The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements. +As depicted in :numref:`fig_qlsofa_hd_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs. + +The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3. + +.. _fig_qlsofa_hd_fle_arch_dual_lut3_mode: + +.. figure:: ./figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg + :scale: 30% + :alt: Logic element schematic + + Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources). + +.. _qlsofa_hd_clb_arch_le_shift_reg_mode: + +Operating mode: Shift-Register +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +As depicted in :numref:`fig_qlsofa_hd_fle_arch_shift_register_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers. + +The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs. + +.. _fig_qlsofa_hd_fle_arch_shift_register_mode: + +.. figure:: ./figures/qlsofa_hd_fle_arch_shift_register_mode.svg + :scale: 30% + :alt: Logic element schematic + + Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources). + +.. _qlsofa_hd_clb_arch_le_soft_adder_mode: + +Operating mode: Soft Adder +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +As depicted in :numref:`fig_qlsofa_hd_fle_arch_soft_adder_mode`, the 4-input LUT can implement an 1-bit adder logic, where carry inputs and outputs are connected through dedicated carry chain wires ``cin`` and ``cout`` across logic elements. This is more delay efficient than implementing adders through the dual LUT3 mode (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`). + +The operating mode is designed to efficiently implement multi-bit adders. + +.. _fig_qlsofa_hd_fle_arch_soft_adder_mode: + +.. figure:: ./figures/qlsofa_hd_fle_arch_soft_adder_mode.svg + :scale: 30% + :alt: Logic element schematic + + Resource usage of the logic element operating in soft adder mode (Grey blocks and lines are unused resources). + +.. _qlsofa_hd_clb_arch_scan_chain: + + +Scan Chain +~~~~~~~~~~ + +There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_qlsofa_hd_clb_arch`. +When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain. +When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs. + +.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`qlsofa_hd_fpga_arch_scan_chain`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst new file mode 100644 index 0000000..f1d079d --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -0,0 +1,82 @@ +.. _qlsofa_hd_fpga_arch: + +Architecture +------------- + +.. _qlsofa_hd_fpga_arch_floorplan: + +Floorplan +^^^^^^^^^ + + +:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. +The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. +I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`). + +.. _fig_qlsofa_hd_fpga_arch: + +.. figure:: ./figures/qlsofa_hd_fpga_arch.svg + :scale: 25% + :alt: Tile-based FPGA architecture + + Tile-based FPGA architecture + + +.. _qlsofa_hd_fpga_arch_tiles: + +Tiles +^^^^^ + +The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built: + +.. table:: FPGA tile type and functionalities + + +------+----------+----------------------------------------------+ + | Type | Capacity | Description | + +======+==========+==============================================+ + | CLB | 144 || Each CLB tile consists of | + | | || - a Configurable Logic Block (CLB) | + | | || - a X-direction Connection Block (CBx) | + | | || - a Y-direction Connection Block (CBy) | + | | || - a Switch Block (SB). | + | | | | + | | || This is the majority tile across the fabric | + | | | to implement logics and registers. | + +------+----------+----------------------------------------------+ + | IO-A | 36 || The type-A I/O is a low-density I/O tile | + | | | which is designed to mainly interface | + | | || the GPIOs of the SoC. | + | | | | + | | || Each I/O-A tile consists of 1 digitial I/O | + | | | cell. | + +------+----------+----------------------------------------------+ + | IO-B | 12 || The type-B I/O is a high-density I/O tile | + | | | which is designed to mainly interface | + | | || the wishbone interface and logic analyzer | + | | | of the SoC. | + | | | | + | | || Each I/O-B tile consists of 9 digitial I/O | + | | | cells. | + +------+----------+----------------------------------------------+ + +.. _qlsofa_hd_fpga_arch_scan_chain: + +Scan-chain +^^^^^^^^^^ + +There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. + +When `Test_en` signal is active, users can + +- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port +- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. + +.. _fig_qlsofa_hd_fabric_scan_chain: + +.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg + :scale: 25% + :alt: Built-in scan-chain across FPGA + + Built-in scan-chain across FPGA + + diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst new file mode 100644 index 0000000..fc2badb --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst @@ -0,0 +1,113 @@ +.. _qlsofa_hd_io_resource: + +I/O Resources +------------- + +Pin Assignment +^^^^^^^^^^^^^^ + +The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. + +Among the 144 I/Os, + +- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs). + +- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`qlsofa_hd_io_resource_debug` and :ref:`qlsofa_hd_io_resource_accelerator` for details. + +.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components. + +.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. + +.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_qlsofa_hd_fpga_io_switch`. + +.. _fig_qlsofa_hd_fpga_io_switch: + +.. figure:: ./figures/qlsofa_hd_fpga_io_switch.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP + + I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface + +.. _io_resource_qlsofa_hd_external_io: + +External I/Os +^^^^^^^^^^^^^ + +A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. + +Full details are summarized in the following table. + +.. table:: SOFA HD FPGA I/O usage and sizes + + +-----------+------------------------------------------------------------------------+-------------+ + | I/O Type | Description | No. of Pins | + +===========+========================================================================+=============+ + | Data I/O | Datapath I/Os of FPGA fabric | 27 | + +-----------+------------------------------------------------------------------------+-------------+ + | CLK | Operating clock of FPGA core | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | RESET | Active-low reset for datapath flip-flops in the FPGA | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | PROG_RESET| Active-low reset for configuration flip-flops in the FPGA | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | CCFF_HEAD | Input of configuation protocol to load bitstream | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | TEST_EN | Activate the test mode of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | Total | | 37 | + +-----------+------------------------------------------------------------------------+-------------+ + +.. _qlsofa_hd_io_resource_accelerator: + +Accelerator Mode +^^^^^^^^^^^^^^^^ + +When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. +:numref:`fig_qlsofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. + +.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected. + +.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator. + +.. _fig_qlsofa_hd_fpga_io_map_wishbone_mode: + +.. figure:: ./figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP when interfacing wishbone bus + + I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus + +.. _qlsofa_hd_io_resource_debug: + +Debug Mode +^^^^^^^^^^ + +When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. +:numref:`fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. + +.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose. + +.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows: + + - all the I/O directionality is set to **input mode**. + - all the output ports is pulled down to **logic ``0``**. + +.. _fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode: + +.. figure:: ./figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP when interfacing logic analyzer + + I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer + + diff --git a/DOC/source/arch/figures/clb_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_clb_arch.svg similarity index 100% rename from DOC/source/arch/figures/clb_arch.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_clb_arch.svg diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg new file mode 100644 index 0000000..75482cb --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 + + switch + + boundary + + + + + + + + + + + + + CCFF_IN + + + + + + + + CCFF_OUT + + + + + + + + FPGA Fabric + + + + + SoC Interface + + + + + + + + base + + + SOC_IN + + + + + SOC_OUT + + + + + + + + + + + + + + + + + FPGA_OUT + + + + + FPGA_IN + + + + + + + + + + + + SOC_DIR + + + + + + + + + + + + + + + + + + + + + + + + + + FF + + + + + + + + + + + + PROG_CLK + + + + + + + + + + + IO_ISOL_N + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + output pin + + + + + input pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fabric_scan_chain.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fabric_scan_chain.svg new file mode 100644 index 0000000..0bf9cc5 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fabric_scan_chain.svg @@ -0,0 +1,320 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-17 17:11:00 +0000 + + fpga_arch + + legend + + + + + + + FPGA + + + + + + + + x + + + + + + + + y + + + + + chain + + + + + CLB + [1][12] + + + + + + + + SC_HEAD + + + + + + + CLB + [1][11] + + + + + + + + + + + … + + + + + + + CLB + [1][2] + + + + + + + + + + CLB + [1][1] + + + + + + + + + + CLB + [2][12] + + + + + + + + + + CLB + [2][11] + + + + + + + + + + + … + + + + + + + CLB + [2][2] + + + + + + + + + + CLB + [2][1] + + + + + + + + + + + + + CLB + [11][12] + + + + + + + + + + CLB + [11][11] + + + + + + + + + + + … + + + + + + + CLB + [11][2] + + + + + + + + + + CLB + [11][1] + + + + + + + + + + CLB + [12][12] + + + + + + + + + + CLB + [12][11] + + + + + + + + + + + … + + + + + + + CLB + [12][2] + + + + + + + + + + CLB + [12][1] + + + + + + + + + + + … + + + + + SC_TAIL + + + + + … + + + + + … + + + + + … + + + + + … + + + + + diff --git a/DOC/source/arch/figures/fle_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch.svg similarity index 100% rename from DOC/source/arch/figures/fle_arch.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch.svg diff --git a/DOC/source/arch/figures/fle_arch_dual_lut3_mode.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_dual_lut3_mode.svg similarity index 100% rename from DOC/source/arch/figures/fle_arch_dual_lut3_mode.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_dual_lut3_mode.svg diff --git a/DOC/source/arch/figures/fle_arch_shift_reg_mode.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_shift_reg_mode.svg similarity index 100% rename from DOC/source/arch/figures/fle_arch_shift_reg_mode.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_shift_reg_mode.svg diff --git a/DOC/source/arch/figures/fle_arch_single_lut4_mode.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_single_lut4_mode.svg similarity index 100% rename from DOC/source/arch/figures/fle_arch_single_lut4_mode.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fle_arch_single_lut4_mode.svg diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_arch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_arch.svg new file mode 100644 index 0000000..59678b3 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_arch.svg @@ -0,0 +1,1089 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-17 16:24:14 +0000 + + fpga_arch + + tiles + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + legend + + + Programmable Fabric + + + + + + + + + + + Routing Tracks + + + + + + + + + + Tile + + + + + + + I/O TileA + + + + + + + + + + + + + + I/O TileB + + + + + + + + + + + 12 + + + + + + + + + 12 + + + + + + + + tile_details + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Switch + Block + + + + + + + Configurable + Logic + Block + + + + + + + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + + + X-direction + Connection + Block + + + + + + + Y-direction + Connection + Block + + + + + + + + + + + diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_map_logic_analyzer_mode.svg similarity index 100% rename from DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_map_logic_analyzer_mode.svg diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_map_wishbone_mode.svg similarity index 100% rename from DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_map_wishbone_mode.svg diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_switch.svg similarity index 100% rename from DOC/source/arch/figures/fpga_io_switch.svg rename to DOC/source/datasheet/sofa_hd/figures/sofa_hd_fpga_io_switch.svg diff --git a/DOC/source/datasheet/sofa_hd/index.rst b/DOC/source/datasheet/sofa_hd/index.rst new file mode 100644 index 0000000..8bff100 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/index.rst @@ -0,0 +1,16 @@ +.. _datasheet_sofa_hd: + SOFA HD + +SOFA HD +------- + +.. toctree:: + :maxdepth: 2 + + sofa_hd_fpga_arch + + sofa_hd_io_resource + + sofa_hd_clb_arch + + sofa_hd_circuit_design diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst new file mode 100644 index 0000000..3a1d824 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst @@ -0,0 +1,36 @@ +.. _sofa_hd_circuit_design: + +Circuit Designs +--------------- + +.. _sofa_hd_circuit_design_io: + +I/O Circuit +^^^^^^^^^^^ + +As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_sofa_hd_fpga_arch`) is an digital I/O cell with + +- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. + + .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! + +- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid + + - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode + - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode + +- An internal configurable memory element to control the direction of I/O cell + +The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where + +- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode + +- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode + +.. _fig_sofa_hd_embedded_io_schematic: + +.. figure:: ./figures/sofa_hd_embedded_io_schematic.svg + :scale: 30% + :alt: Schematic of embedded I/O cell used in FPGA + + Schematic of embedded I/O cell used in FPGA diff --git a/DOC/source/arch/clb_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_clb_arch.rst similarity index 61% rename from DOC/source/arch/clb_arch.rst rename to DOC/source/datasheet/sofa_hd/sofa_hd_clb_arch.rst index ae830d9..fb0aaea 100644 --- a/DOC/source/arch/clb_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_clb_arch.rst @@ -1,26 +1,26 @@ -.. _clb_arch: +.. _sofa_hd_clb_arch: Configurable Logic Block ------------------------ -.. _clb_arch_generality: +.. _sofa_hd_clb_arch_generality: Generality ~~~~~~~~~~ -Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_clb_arch`. +Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_sofa_hd_clb_arch`. All the pins of the LEs are directly wired to CLB pins without a local routing architecture. Feedback connections between LEs are implemented by the global routing architecture outside the CLBs. -.. _fig_clb_arch: +.. _fig_sofa_hd_clb_arch: -.. figure:: ./figures/clb_arch.svg +.. figure:: ./figures/sofa_hd_clb_arch.svg :scale: 20% :alt: Configurable Logic Block schematic Configurable logic block schematic -.. _clb_arch_le: +.. _sofa_hd_clb_arch_le: Multi-mode Logic Element ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -28,14 +28,14 @@ Multi-mode Logic Element Physical Implementation ^^^^^^^^^^^^^^^^^^^^^^^ -As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of +As shown in :numref:`fig_sofa_hd_fle_arch`, each Logic Element (LE) consists of - a fracturable 4-input Look-Up Table (LUT) - two D-type Flip-Flops (FF) -.. _fig_fle_arch: +.. _fig_sofa_hd_fle_arch: -.. figure:: ./figures/fle_arch.svg +.. figure:: ./figures/sofa_hd_fle_arch.svg :scale: 30% :alt: Logic element schematic @@ -43,71 +43,71 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of The LE can operate in different modes to map logic function efficiently -- 4-input LUT and single FF (see details in :ref:`clb_arch_le_single_lut4_mode`). -- Dual 3-input LUTs and 2 FFs (see details in :ref:`clb_arch_le_dual_lut3_mode`). -- 2-bit shift registers (see details in :ref:`clb_arch_le_shift_reg_mode`). +- 4-input LUT and single FF (see details in :ref:`sofa_hd_clb_arch_le_single_lut4_mode`). +- Dual 3-input LUTs and 2 FFs (see details in :ref:`sofa_hd_clb_arch_le_dual_lut3_mode`). +- 2-bit shift registers (see details in :ref:`sofa_hd_clb_arch_le_shift_reg_mode`). -.. _clb_arch_le_single_lut4_mode: +.. _sofa_hd_clb_arch_le_single_lut4_mode: Operating mode: LUT4 + FF ^^^^^^^^^^^^^^^^^^^^^^^^^ The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements. -As depicted in :numref:`fig_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic. +As depicted in :numref:`fig_sofa_hd_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic. The operating mode is designed to efficiently implement 4-input functions. -.. _fig_fle_arch_single_lut4_mode: +.. _fig_sofa_hd_fle_arch_single_lut4_mode: -.. figure:: ./figures/fle_arch_single_lut4_mode.svg +.. figure:: ./figures/sofa_hd_fle_arch_single_lut4_mode.svg :scale: 30% :alt: Logic element schematic Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources). -.. _clb_arch_le_dual_lut3_mode: +.. _sofa_hd_clb_arch_le_dual_lut3_mode: Operating mode: Dual-LUT3 ^^^^^^^^^^^^^^^^^^^^^^^^^ The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements. -As depicted in :numref:`fig_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs. +As depicted in :numref:`fig_sofa_hd_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs. The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3. -.. _fig_fle_arch_dual_lut3_mode: +.. _fig_sofa_hd_fle_arch_dual_lut3_mode: -.. figure:: ./figures/fle_arch_dual_lut3_mode.svg +.. figure:: ./figures/sofa_hd_fle_arch_dual_lut3_mode.svg :scale: 30% :alt: Logic element schematic Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources). -.. _clb_arch_le_shift_reg_mode: +.. _sofa_hd_clb_arch_le_shift_reg_mode: Operating mode: Shift-Register ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -As depicted in :numref:`fig_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers. +As depicted in :numref:`fig_sofa_hd_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers. The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs. -.. _fig_fle_arch_shift_reg_mode: +.. _fig_sofa_hd_fle_arch_shift_reg_mode: -.. figure:: ./figures/fle_arch_shift_reg_mode.svg +.. figure:: ./figures/sofa_hd_fle_arch_shift_reg_mode.svg :scale: 30% :alt: Logic element schematic Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources). -.. _clb_arch_scan_chain: +.. _sofa_hd_clb_arch_scan_chain: Scan Chain ~~~~~~~~~~ -There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_clb_arch`. +There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_sofa_hd_clb_arch`. When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain. When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs. -.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`fpga_arch_scan_chain`. +.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`sofa_hd_fpga_arch_scan_chain`. diff --git a/DOC/source/arch/fpga_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst similarity index 82% rename from DOC/source/arch/fpga_arch.rst rename to DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst index c59304e..5f503c9 100644 --- a/DOC/source/arch/fpga_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst @@ -1,30 +1,31 @@ -.. _fpga_arch: +.. _sofa_hd_fpga_arch: -FPGA Overview +Architecture ------------- -.. _fpga_arch_overview: -Architecture Overview -~~~~~~~~~~~~~~~~~~~~~ +.. _sofa_hd_fpga_arch_floorplan: -:numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. +Floorplan +^^^^^^^^^ + +:numref:`fig_sofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. -I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`io_resource`). +I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`sofa_hd_io_resource`). -.. _fig_fpga_arch: +.. _fig_sofa_hd_fpga_arch: -.. figure:: ./figures/fpga_arch.svg +.. figure:: ./figures/sofa_hd_fpga_arch.svg :scale: 25% :alt: Tile-based FPGA architecture Tile-based FPGA architecture -.. _fpga_arch_tiles: +.. _sofa_hd_fpga_arch_tiles: Tiles -~~~~~ +^^^^^ The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built: @@ -58,21 +59,21 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra | | | cells. | +------+----------+----------------------------------------------+ -.. _fpga_arch_scan_chain: +.. _sofa_hd_fpga_arch_scan_chain: Scan-chain -~~~~~~~~~~ +^^^^^^^^^^ -There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`clb_arch_scan_chain`), as illustrated in :numref:`fig_fabric_scan_chain`. +There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`sofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_sofa_hd_fabric_scan_chain`. When `Test_en` signal is active, users can - overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port - readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. -.. _fig_fabric_scan_chain: +.. _fig_sofa_hd_fabric_scan_chain: -.. figure:: ./figures/fabric_scan_chain.svg +.. figure:: ./figures/sofa_hd_fabric_scan_chain.svg :scale: 25% :alt: Built-in scan-chain across FPGA diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst new file mode 100644 index 0000000..48f29a3 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst @@ -0,0 +1,109 @@ +.. _sofa_hd_io_resource: + +I/O Resources +------------- + +Pin Assignment +^^^^^^^^^^^^^^ + +The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_sofa_hd_fpga_io_switch`. + +Among the 144 I/Os, + +- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs). + +- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`sofa_hd_io_resource_debug` and :ref:`sofa_hd_io_resource_accelerator` for details. + +.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components. + +.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. + +.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_sofa_hd_fpga_io_switch`. + +.. _fig_sofa_hd_fpga_io_switch: + +.. figure:: ./figures/sofa_hd_fpga_io_switch.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP + + I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface + +.. _io_resource_sofa_hd_external_io: + +External I/Os +^^^^^^^^^^^^^ + +A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os. + +Full details are summarized in the following table. + +.. table:: SOFA HD FPGA I/O usage and sizes + + +-----------+------------------------------------------------------------------------+-------------+ + | I/O Type | Description | No. of Pins | + +===========+========================================================================+=============+ + | Data I/O | Datapath I/Os of FPGA fabric | 29 | + +-----------+------------------------------------------------------------------------+-------------+ + | CLK | Operating clock of FPGA core | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | CCFF_HEAD | Input of configuation protocol to load bitstream | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | TEST_EN | Activate the test mode of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | Total | | 37 | + +-----------+------------------------------------------------------------------------+-------------+ + +.. _sofa_hd_io_resource_accelerator: + +Accelerator Mode +^^^^^^^^^^^^^^^^ + +When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. +:numref:`fig_sofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. + +.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected. + +.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator. + +.. _fig_sofa_hd_fpga_io_map_wishbone_mode: + +.. figure:: ./figures/sofa_hd_fpga_io_map_wishbone_mode.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP when interfacing wishbone bus + + I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus + +.. _sofa_hd_io_resource_debug: + +Debug Mode +^^^^^^^^^^ + +When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. +:numref:`fig_sofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. + +.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose. + +.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows: + + - all the I/O directionality is set to **input mode**. + - all the output ports is pulled down to **logic ``0``**. + +.. _fig_sofa_hd_fpga_io_map_logic_analyzer_mode: + +.. figure:: ./figures/sofa_hd_fpga_io_map_logic_analyzer_mode.svg + :scale: 20% + :alt: I/O arrangement of FPGA IP when interfacing logic analyzer + + I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer + + diff --git a/DOC/source/device/dc_ac_character.rst b/DOC/source/device/dc_ac_character.rst deleted file mode 100644 index 1e7b3b2..0000000 --- a/DOC/source/device/dc_ac_character.rst +++ /dev/null @@ -1,75 +0,0 @@ -.. _dc_ac_character: - -DC and AC Characteristics -------------------------- - -Each FPGA device contains 37 external I/O pins, whose details are summarized in the following tables. - -I/O usage and port information -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. table:: I/O usage and sizes - - +-----------+------------------------------------------------------------------------+-------------+ - | I/O Type | Description | No. of Pins | - +===========+========================================================================+=============+ - | Data I/O | Datapath I/Os of FPGA fabric | 29 | - +-----------+------------------------------------------------------------------------+-------------+ - | Clk | Operating clock of FPGA core | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | CCin | Input of configuation protocol to load bitstream | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | CCout | Output of configuration protocol to read back bitstream | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | TestEn | Activate the test mode of FPGA fabric | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 | - +-----------+------------------------------------------------------------------------+-------------+ - | Total | | 37 | - +-----------+------------------------------------------------------------------------+-------------+ - -Recommended Operating Conditions -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. table:: Recommended Operating Conditions - - +----------+------------------------------+------+---------+------+-------+ - | Symbol | Description | Min | Typical | Max | Units | - +==========+==============================+======+=========+======+=======+ - | VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V | - +----------+------------------------------+------+---------+------+-------+ - | VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V | - +----------+------------------------------+------+---------+------+-------+ - | V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V | - +----------+------------------------------+------+---------+------+-------+ - | I_in | Maximum current through pins | N/A | TBD | TBD | mA | - +----------+------------------------------+------+---------+------+-------+ - | f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz | - +----------+------------------------------+------+---------+------+-------+ - -.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1` -.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`. - -Typical AC Characteristics -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. table:: Typical AC characteristics for FPGA I/Os - - +-----------------+-------------------------------------------+------+------+-------+ - | Symbol | Description | Min | Max | Units | - +=================+===========================================+======+======+=======+ - | V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V | - +-----------------+-------------------------------------------+------+------+-------+ - | V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V | - +-----------------+-------------------------------------------+------+------+-------+ - | I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA | - +-----------------+-------------------------------------------+------+------+-------+ - | I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA | - +-----------------+-------------------------------------------+------+------+-------+ - diff --git a/DOC/source/device/device_resource.rst b/DOC/source/device/device_resource.rst deleted file mode 100644 index ea78fb4..0000000 --- a/DOC/source/device/device_resource.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. _device_resource: - -Device Resources ----------------- - -.. _device_resource_hd_fpga: - -High-Density FPGA -~~~~~~~~~~~~~~~~~ - -The High Density (HD) FPGA is an embedded FPGA built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD `_). - -.. table:: Logic capacity of High Density (HD) FPGA IP - - +-------------------------------+------------+ - | Resource Type | Capacity | - +===============================+============+ - | Look-Up Tables [1]_ | 1152 | - +-------------------------------+------------+ - | Flip-flops | 2304 | - +-------------------------------+------------+ - | Max. Configuration Speed [2]_ | 50MHz | - +-------------------------------+------------+ - | Max. Operating Speed [2]_ | 50MHz | - +-------------------------------+------------+ - | User I/O Pins [3]_ | 144 | - +-------------------------------+------------+ - | Max. I/O Speed [2]_ | 33MHz | - +-------------------------------+------------+ - | Core Voltage | 1.8V | - +-------------------------------+------------+ - -.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. - -.. [2] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK `_. Higher speed may be expected when a high-speed GPIO cell is available. - -.. [3] I/Os are divided into two groups: GPIO and embedded I/O. See details in :ref:`io_resource`. - diff --git a/DOC/source/device/hd_fpga/hd_device_comp.rst b/DOC/source/device/hd_fpga/hd_device_comp.rst new file mode 100644 index 0000000..940efe4 --- /dev/null +++ b/DOC/source/device/hd_fpga/hd_device_comp.rst @@ -0,0 +1,41 @@ +.. _hd_fpga_device_comparison: + +Device Comparison +----------------- + +The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD `_). + +.. table:: Logic capacity of High Density (HD) FPGA IPs + + +-------------------------------+------------+-----------+ + | Resource/Capacity | SOFA HD | QLSOFA HD | + +===============================+============+===========+ + | Look-Up Tables [1]_ | 1152 | 1152 | + +-------------------------------+------------+-----------+ + | Flip-flops | 2304 | 2304 | + +-------------------------------+------------+-----------+ + | Soft Adders [2]_ | N/A | 1152 | + +-------------------------------+------------+-----------+ + | Routing Channel Width [3]_ | 40 | 60 | + +-------------------------------+------------+-----------+ + | Max. Configuration Speed [4]_ | 50MHz | 50MHz | + +-------------------------------+------------+-----------+ + | Max. Operating Speed [4]_ | 50MHz | 50 MHz | + +-------------------------------+------------+-----------+ + | User I/O Pins [5]_ | 144 | 144 | + +-------------------------------+------------+-----------+ + | Max. I/O Speed [4]_ | 33MHz | 33 MHz | + +-------------------------------+------------+-----------+ + | Core Voltage | 1.8V | 1.8V | + +-------------------------------+------------+-----------+ + +.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. + +.. [2] counted by 3-input Look-Up Tables (LUTs) that are organized as a carry chain + +.. [3] counted by number of uni-directional routing tracks per tile + +.. [4] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK `_. Higher speed may be expected when a high-speed GPIO cell is available. + +.. [5] I/Os are divided into two groups: GPIOs and embedded I/Os. + diff --git a/DOC/source/device/hd_fpga/hd_device_dcac.rst b/DOC/source/device/hd_fpga/hd_device_dcac.rst new file mode 100644 index 0000000..91baa82 --- /dev/null +++ b/DOC/source/device/hd_fpga/hd_device_dcac.rst @@ -0,0 +1,44 @@ +.. _hd_fpga_dc_ac_character: + +DC and AC Characteristics +------------------------- + +Recommended Operating Conditions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. table:: Recommended Operating Conditions + + +----------+------------------------------+------+---------+------+-------+ + | Symbol | Description | Min | Typical | Max | Units | + +==========+==============================+======+=========+======+=======+ + | VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V | + +----------+------------------------------+------+---------+------+-------+ + | VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V | + +----------+------------------------------+------+---------+------+-------+ + | V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V | + +----------+------------------------------+------+---------+------+-------+ + | I_in | Maximum current through pins | N/A | TBD | TBD | mA | + +----------+------------------------------+------+---------+------+-------+ + | f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz | + +----------+------------------------------+------+---------+------+-------+ + +.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1` +.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`. + +Typical AC Characteristics +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. table:: Typical AC characteristics for FPGA I/Os + + +-----------------+-------------------------------------------+------+------+-------+ + | Symbol | Description | Min | Max | Units | + +=================+===========================================+======+======+=======+ + | V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V | + +-----------------+-------------------------------------------+------+------+-------+ + | V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V | + +-----------------+-------------------------------------------+------+------+-------+ + | I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA | + +-----------------+-------------------------------------------+------+------+-------+ + | I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA | + +-----------------+-------------------------------------------+------+------+-------+ + diff --git a/DOC/source/device/hd_fpga/index.rst b/DOC/source/device/hd_fpga/index.rst new file mode 100644 index 0000000..a6802e3 --- /dev/null +++ b/DOC/source/device/hd_fpga/index.rst @@ -0,0 +1,12 @@ +HD FPGAs +-------- + +.. _device_family_hd_fpga: + HD FPGA Family + +.. toctree:: + :maxdepth: 2 + + hd_device_comp + + hd_device_dcac diff --git a/DOC/source/device/index.rst b/DOC/source/device/index.rst index e2f9d8c..6f733f4 100644 --- a/DOC/source/device/index.rst +++ b/DOC/source/device/index.rst @@ -1,11 +1,9 @@ -.. _device: - Device Datasheet +.. _device_family: + Device Family .. toctree:: :maxdepth: 2 - device_overview + introduction - device_resource - - dc_ac_character + hd_fpga/index diff --git a/DOC/source/device/device_overview.rst b/DOC/source/device/introduction.rst similarity index 89% rename from DOC/source/device/device_overview.rst rename to DOC/source/device/introduction.rst index 4f7680a..24f163e 100644 --- a/DOC/source/device/device_overview.rst +++ b/DOC/source/device/introduction.rst @@ -1,7 +1,7 @@ -.. _device_overview: +.. _device_family_introduction: -General Description -------------------- +Introduction +------------ All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII. All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. diff --git a/DOC/source/index.rst b/DOC/source/index.rst index f9fca98..cbf7d6e 100644 --- a/DOC/source/index.rst +++ b/DOC/source/index.rst @@ -7,15 +7,15 @@ Welcome to SKywater-OpenFPGA documentation! =========================================== .. toctree:: - :caption: Device Datasheet + :caption: Device Family device/index .. toctree:: :maxdepth: 2 - :caption: FPGA Architecture + :caption: Datasheets - arch/index + datasheet/index .. toctree:: :maxdepth: 2 diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json index abbff5b..63cf9d2 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -46,13 +46,13 @@ "caravel_pin_index": ["10:4"] }, { - "fpga_pin_type": "prog_reset", + "fpga_pin_type": "pReset", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["3:3"] }, { - "fpga_pin_type": "reset", + "fpga_pin_type": "Reset", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["2:2"] diff --git a/HDL/common/custom_cell_mux_primitive_generator.py b/HDL/common/custom_cell_mux_primitive_generator.py new file mode 100644 index 0000000..45b8c88 --- /dev/null +++ b/HDL/common/custom_cell_mux_primitive_generator.py @@ -0,0 +1,179 @@ +##################################################################### +# Python script generate Verilog codes for the primitive modules +# that is used to build routing multiplexers +# The Verilog codes will exploit the custom cells built for MUX primitives +# including: +# - 2-input MUX +# - 3-input MUX +# - Skywater MUX2 standard cell +##################################################################### + +import os +from os.path import dirname, abspath, isfile +import shutil +import re +import argparse +import logging +import json + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG) + +##################################################################### +# Parse the options +# - OpenFPGA root path is a manadatory option +##################################################################### +parser = argparse.ArgumentParser( + description='Generator for custom cells of routing multiplexer primitives') +parser.add_argument('--template_netlist', required=True, + help='Specify template verilog netlist') +parser.add_argument('--output_verilog', required=True, + help='Specify output verilog file path') +args = parser.parse_args() + +##################################################################### +# Check options: +# - Input file must be valid +# Otherwise, error out +# - Remove any output file if already exist +# TODO: give a warning when remove files +##################################################################### +if not isfile(args.template_netlist): + logging.error("Invalid template netlist: " + args.template_netlist + "\nFile does not exist!\n") + exit(1) +if isfile(args.output_verilog): + logging.warn("Remove existing output netlist: " + args.output_verilog + "!\n") + os.remove(args.output_verilog) + +##################################################################### +# Open the template Verilog netlist and start modification +##################################################################### +logging.info("Converting template netlist:"+ args.template_netlist) +logging.info(" To custom cell netlist:"+ args.output_verilog) +# Create output file handler +custom_nlist = open(args.output_verilog, "w") + +####################################################################### +# A function to generate Verilog codes for a MUX3 custom cell +# Given an input index +def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index): + lines = [] + + lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(") + lines.append("\t .Q1(in[" + str(first_input_index) + "]),") + lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") + lines.append("\t .Q3(in[" + str(first_input_index + 2) + "]),") + lines.append("\t .S0(mem[" + str(first_input_index) + "]),") + lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),") + lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),") + lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),") + lines.append("\t .S2(mem[" + str(first_input_index + 2) + "]),") + lines.append("\t .S2B(mem_inv[" + str(first_input_index + 2) + "]),") + lines.append("\t .Z(out[0])") + lines.append("\t );") + + return lines + +####################################################################### +# A function to generate Verilog codes for a MUX3 custom cell +# Given an input index +def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index): + lines = [] + + lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(") + lines.append("\t .Q1(in[" + str(first_input_index) + "]),") + lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") + lines.append("\t .S0(mem[" + str(first_input_index) + "]),") + lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),") + lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),") + lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),") + lines.append("\t .Z(out[0])") + lines.append("\t );") + + return lines + + +####################################################################### +# A function to output custom cells of multiplexing structure to a file +# based on the input size and memory size +# - If the memory size is 1, the input size should be 2 +# In this case, an standard cell will be outputted +# - If the memory size is larger than 1, the input size should be the same +# as memory size. In this case, we will output custom cells +def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size): + lines = [] + if (1 == mem_size): + assert(2 == input_size) + # Output a standard cell, currently we support HD cell MUX2 + lines.append("\tsky130_fd_sc_hd_mux2_1 sky130_fd_sc_hd_mux2_1_0(") + lines.append("\t .A1(in[0]),") + lines.append("\t .A0(in[1]),") + lines.append("\t .S(mem[0]),") + lines.append("\t .X(out[0])") + lines.append("\t );") + else: + assert(1 < mem_size) + assert(mem_size == input_size) + # Currently we support MUX2 and MUX3 custom cells + # - If the input size is an odd number, we will use + # - 1 MUX3 cell + # - a few MUX2 cells + if (1 == input_size % 2): + assert(3 <= input_size) + for line in generate_verilog_codes_custom_cell_mux3(0, 0): + lines.append(line) + for mux2_inst in range(int((input_size - 3) / 2)): + for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst): + lines.append(line) + # - If the input size is an even number, we will use + # - a few MUX2 cells + else: + assert (0 == input_size % 2) + for mux2_inst in range(int(input_size / 2)): + for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst): + lines.append(line) + + # Output lines to file + for line in lines: + custom_nlist.write(line + "\n") + +# Read line by line from template netlist +with open(args.template_netlist, "r") as wp: + template_nlist = wp.readlines() + # A flag for write the current line or skip + output_action = "copy" + input_size = 0 + mem_size = 0 + for line_num, curr_line in enumerate(template_nlist): + # If the current line satisfy the following conditions + # It should be modified and outputted to custom netlist + # Other lines can be directly copied to custom netlist + line2output = curr_line + # Once current line starts with a module definition + # Find the input size and memory size + if (curr_line.startswith("module ")): + input_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][0]) + mem_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][1]) + assert(input_size > 0) + assert(mem_size > 0) + # Change status indicating that we are now inside a module + output_action = "copy" + + # If a line contains the keyword TGATE + # we will bypass all the lines until reach the endmodule line + if (curr_line.startswith("\tTGATE TGATE")): + output_action = "skip" + + # Reaching the end of the current module + # Now output the custom cell instanciation + if (curr_line.startswith("endmodule")): + write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size) + output_action = "copy" + + if ("skip" != output_action): + custom_nlist.write(line2output) + +custom_nlist.close() +logging.info("Done") diff --git a/MSIM/common/run_post_pnr_msim_test.py b/MSIM/common/run_post_pnr_msim_test.py index 54d5e25..83942d4 100644 --- a/MSIM/common/run_post_pnr_msim_test.py +++ b/MSIM/common/run_post_pnr_msim_test.py @@ -121,16 +121,24 @@ for line in vsim_log_file: # Check errors from self-testing testbench output if line.startswith("# Simulation finish with") : num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1]) - num_err_lines_found = num_err_lines_found + 1 + num_err_lines_found += 1 if (0 < num_sim_err) : logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") # Add to total errors - num_err = num_err + num_sim_err + num_err += num_sim_err + if line.startswith("# Simulation Failed with") : + print (line) + num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1]) + num_err_lines_found += 1 + if (0 < num_sim_err) : + logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") + # Add to total errors + num_err += num_sim_err # Check total errors by Modelsim if line.startswith("# Errors:") : num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1]) - num_err_lines_found = num_err_lines_found + 1 - num_err = num_err + num_msim_err + num_err_lines_found += 1 + num_err += num_msim_err vsim_log_file.close() diff --git a/README.md b/README.md index 3b24f9d..a0870a8 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ -# Skywater + OpenFPGA: Open-Source FPGAs +# SOFA [![linux_build](https://github.com/LNIS-Projects/skywater-openfpga/workflows/linux_build/badge.svg)](https://github.com/LNIS-Projects/skywater-openfpga/actions) [![Documentation Status](https://readthedocs.org/projects/skywater-openfpga/badge/?version=latest)](https://skywater-openfpga.readthedocs.io/en/latest/?badge=latest) ## Introduction -FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA +SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework ## Quick Start diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf deleted file mode 100644 index 9c68de0..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf deleted file mode 100644 index 32618a5..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf deleted file mode 100644 index 6fe9240..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,54 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/prepnr -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v -bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v -bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v -bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v -bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v -bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v -bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench1_top = and2_latch -bench2_top = bin2bcd -bench3_top = counter -bench4_top = routing_test -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5_top = rs_decoder_top -bench6_top = top_module -bench7_top = and2_or2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf deleted file mode 100644 index 3c1d0fc..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf deleted file mode 100644 index bd6bd45..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf deleted file mode 100644 index 69f70a1..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,54 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v -bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v -bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v -bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v -bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v -bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v -bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench1_top = and2_latch -bench2_top = bin2bcd -bench3_top = counter -bench4_top = routing_test -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5_top = rs_decoder_top -bench6_top = top_module -bench7_top = and2_or2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/TESTBENCH/common/ccff_test_post_pnr.v b/TESTBENCH/common/ccff_test_post_pnr_v1.0.v similarity index 100% rename from TESTBENCH/common/ccff_test_post_pnr.v rename to TESTBENCH/common/ccff_test_post_pnr_v1.0.v diff --git a/TESTBENCH/common/ccff_test_post_pnr_v1.1.v b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v new file mode 100644 index 0000000..978b08b --- /dev/null +++ b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:54de2236bc41e29dfa92693844fc6c1f4d50a3b61f4b0055c9db9ac8877ace49 +size 6051 diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index cebd223..5bfa734 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ae0fb278944fcfc542a395b998e06e1c5d473df8d7d192ff9a386f1ba596ee4 -size 7630 +oid sha256:89b4703e97499ddd03efb70998f547462d7a8fa5d27e2c2d2af132b2050e195d +size 7942 diff --git a/TESTBENCH/common/scff_test_post_pnr.v b/TESTBENCH/common/scff_test_post_pnr_v1.0.v similarity index 100% rename from TESTBENCH/common/scff_test_post_pnr.v rename to TESTBENCH/common/scff_test_post_pnr_v1.0.v diff --git a/TESTBENCH/common/scff_test_post_pnr_v1.1.v b/TESTBENCH/common/scff_test_post_pnr_v1.1.v new file mode 100644 index 0000000..1b1a7b1 --- /dev/null +++ b/TESTBENCH/common/scff_test_post_pnr_v1.1.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dcad9b2185f4571e82799aca46235e4193c3744c41b4ed6507ea2f339c9d894a +size 5872 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index c1b7265..e40f43e 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3140f41d14f1046308ebd07b6527c4ec781ab3c18e63b237aba9b435b9c044de +size 1239 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 8851916..2781b69 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb -size 1478 +oid sha256:9d2003a31c42e9558a77f3891b6284affed509e22d38dbb150f475db968c5f8e +size 1343 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 694c7f1..731e086 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Nov 22 13:37:06 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:6395e2f33f3dcb8dad1c92fa0659bc4b842b3495d683add90e50d942e28b6ef1 +size 1235 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 7354521..f9dd991 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573 -size 1474 +oid sha256:ec87f38ebc0e4f795a0a72b760f6181288ef6f7cc72f7708ec21d77a1ea8c28d +size 1339 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 24d1f7b..bf40134 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:0168df4405980eb7be0f0231735794d86c514199126d0941f043ba38905d0c4f +size 1227 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 40df803..1e21a4f 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f6df360605df5a436036afc2ccf3b950ce42b3c9ea396350cd4ebbb4d705b9d -size 1466 +oid sha256:3fc3f03b263ff267b9543c09f338222e9e9950978915a10a16825decd8deab4c +size 1331 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 0f03de9..30a2005 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f3da10525b0dff707611379ed6ae1348c294eae1a8cd31499ce2e35dde3beaab -size 1329 +oid sha256:5b1dbfb9b52a4e87e544773b46710111d2a53c24922de3e10eefd82c7d280f0b +size 1199 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 838b868..386cac1 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06bb3d6a1ee52298d3ac59ad73f16132b268c013b3cb411d0dfe6f033f6aed36 -size 1488 +oid sha256:f5fe62252b7eae6cd437a4fde8a18dcdcc61e629ab847b6bffa2d8d0d8dc60b4 +size 1353 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 3f49591..79c523c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:54 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:9a2a5d743a10211cd55496c15a559690e5a09a328edcb0942d901ba5e5df48b8 +size 1243 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 7139452..e440cab 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf -size 1482 +oid sha256:a18b7fab25c736e3d465a51353672d7bc5dc7e693145fee2837afc1d11b78289 +size 1347 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index ae327f8..1edcd07 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f25455fe75150d87bcfb386c5c953172a1712655ec1e38017d22aeb062314a6d -size 1328 +oid sha256:98d430047e77dd1e59a84fd4fdc368b229f29e27ae0354657e166db51e2f56a3 +size 1198 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 5694280..8783bb0 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c3b64adf49892e8d7e7263273e76b566cb1f0922d404c224d550136d43b49178 -size 1487 +oid sha256:5dd9f4ffe36c1f5ac05ff49da29ec5541913f2e2efce7cf7a4c7e1cb9120264e +size 1352 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v new file mode 100644 index 0000000..ca377b7 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:32e7a27472ef1501fec8765f8a7beb44ab61c84c514a5f63801840cfdec20eb7 +size 1272 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..5d0b93a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c2067d21d21d3666ebe52b8de512bf06020ab395b65304387709e166e1d43a23 +size 1376 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v new file mode 100644 index 0000000..b93bc4a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ee2934fe5c3048ac3655a3cc6213f176d83c3495aef7428904ad229f39d424a0 +size 1268 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..c87613f --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1707e2d2da1c2eba04f17079d9d9144b71be24bf19b9d99c83ceefc5d46d6afd +size 1372 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v new file mode 100644 index 0000000..0fe63cd --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:35a893d7106b66061ef6c45570ba26c5eb2cc31c1ba667193e01003e1a3c8294 +size 1260 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..d6c6337 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3cfd0b49a75dbcc308f61212ed162d2c74c9343bffe35d78cb39fa553507b559 +size 1364 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..114dfab --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fe32ecd75d97fefe74d1e1e01713ed38098f845cc37aad617b161e64a05a4e36 +size 1216 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..222f122 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cedd3fbe2dc2158e46da28ab3b630b45571f7015b89f29391b092bb3860fdbcc +size 1386 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..a37047e --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7dbfbefcae891ea972982503967a7dc838843bd86ff134873a38da4a1c4b4a1f +size 1276 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..d5bbb87 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b5388c9df5e22b40644563abea84f530445b17a43673499bcfcb9680acf5aa66 +size 1380 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..3c6c896 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8cb80347043fd1a8fab62f8963bf174668951941f6a60e3ba6db9c2a0f439b07 +size 1215 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..73ead6b --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e7a163317878eb9295a02108efc9a8e7c3f4a5485aa05e03bd29b40445d88d88 +size 1385