From aff43bf473f781d524c29b687e618916ac9da30f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 28 Nov 2020 17:37:36 -0700 Subject: [PATCH] [Doc] Add README to HDL common files --- HDL/common/README.md | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 HDL/common/README.md diff --git a/HDL/common/README.md b/HDL/common/README.md new file mode 100644 index 0000000..01a748d --- /dev/null +++ b/HDL/common/README.md @@ -0,0 +1,10 @@ +# Skywater PDK +This directory contains the HDL netlists and code generator for FPGA fabrics. + +- **caravel_fpga_wrapper_hd.v**: The wrapper for FPGA fabric to interface the Caravel SoC, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. **This file is automatically generated by a Python script** +- **caravel_defines.v**: The parameters required for Caravel wrapper HDL codes +- **caravel_fpga_wrapper_hd_template.v**: The template HDL codes for the wrapper +- **digital_io_hd.v**: the I/O cell used by High-density FPGA, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. +- **sky130_fd_sc_hd_wrapper.v**: Wrapper codes for the standard cells from the Skywater 130nm Foundry High-Density Standard Cell Library +- **skywater_function_verification.v**: Include pre-processing flags to enable functional verification for FPGAs +- **wrapper_lines_generator.py**: Python script to generate the wrapper *caravel\_fpga\_wrapper\_hd.v*