diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg index 8b7cb01..eba2802 100644 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg @@ -1,6 +1,6 @@ - + @@ -23,8 +23,8 @@ - Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 - + Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000 + schematic_timing 图层 1 @@ -392,6 +392,11 @@ A + + + B + + diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst index c5cfbf4..7d2745a 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst @@ -8,12 +8,12 @@ Timing Annotation Configurable Logic Block ^^^^^^^^^^^^^^^^^^^^^^^^ -The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. +The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. .. _fig_qlsofa_hd_fle_arch_timing: .. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in QLSOFA HD FPGA Schematic of a logic element used in QLSOFA HD FPGA @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> B | 0.60 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | B -> LUT3_out[0] | 0.32 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.90 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.62 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | B -> LUT3_out[1] | 0.33 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.17 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.89 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 1.21 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out | 0.79 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,8 +68,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. - .. _qlsofa_hd_timing_io: I/O Block diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg index 8b7cb01..eba2802 100644 --- a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg @@ -1,6 +1,6 @@ - + @@ -23,8 +23,8 @@ - Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 - + Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000 + schematic_timing 图层 1 @@ -392,6 +392,11 @@ A + + + B + + diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst index 65fef7a..d48623a 100644 --- a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: .. _fig_sofa_chd_fle_arch_timing: .. figure:: ./figures/sofa_chd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in SOFA CHD FPGA Schematic of a logic element used in SOFA CHD FPGA @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> B | 0.60 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | B -> LUT3_out[0] | 0.32 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.90 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.62 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | B -> LUT3_out[1] | 0.33 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.17 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.89 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 1.21 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out | 0.79 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,7 +68,6 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. .. _sofa_chd_timing_io: diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst index 731eb72..104a7da 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` .. _fig_sofa_hd_fle_arch_timing: .. figure:: ./figures/sofa_hd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in SOFA HD FPGA Schematic of a logic element used in SOFA HD FPGA @@ -25,25 +25,25 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> LUT3_out[0] | 0.30 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.86 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.59 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in2 -> LUT3_out[1] | 0.31 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.14 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.86 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 0.58 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in3 -> LUT4_out | 0.51 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,8 +66,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. - .. _sofa_hd_timing_io: I/O Block