diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 90e3c94..374fce6 100644
--- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -369,7 +369,7 @@ foundry middle-speed (ms) standard cell library
   </direct_connection>
   <tile_annotations>
     <global_port name="clk" is_clock="true" default_val="0">
-      <tile name="clb" port="clk" x="-1" y="-1"/>
+      <tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
       <tile name="io_top" port="clk" x="-1" y="-1"/>
       <tile name="io_right" port="clk" x="-1" y="-1"/>
       <tile name="io_bottom" port="clk" x="-1" y="-1"/>
diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index f141b76..1c7155e 100644
--- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -170,7 +170,7 @@ Authors: Xifan Tang
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <output name="cout_copy" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
+      <clock name="clk" num_pins="4"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
         <fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
         <fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
@@ -447,7 +447,7 @@ Authors: Xifan Tang
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <output name="cout_copy" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
+      <clock name="clk" num_pins="4"/>
         <!-- Describe fracturable logic element.  
           Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
           The outputs of the fracturable logic element can be optionally registered