From abea1a8aa0a5922aecd5ea3a80d64c6799b46a51 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 17 Mar 2023 10:23:05 -0600
Subject: [PATCH] Changed fpga_top to fpga_core

---
 SOFA_A/CommonFiles/restructure_fabric_sofa_a.py           | 3 +++
 .../FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v           | 2 +-
 .../FPGA88_SOFA_A_verilog/SRC/{fpga_top.v => fpga_core.v} | 2 +-
 SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt     | 2 +-
 .../FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_floorplan.svg | 8 ++++----
 5 files changed, 10 insertions(+), 7 deletions(-)
 rename SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/{fpga_top.v => fpga_core.v} (99%)

diff --git a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
index c96b7ad..25f04eb 100644
--- a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
+++ b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
@@ -255,6 +255,9 @@ def main():
     create_global_feedthrough(fpga, "prog_reset", instance_map)
     create_global_feedthrough(fpga, "test_enable", instance_map)
 
+    # Change top module name
+    fpga.top_module.name = "fpga_core"
+
     save_netlist(fpga)
     filename = SVG_DIR + f"{PROJ_NAME}_floorplan.svg"
     save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
index 969d686..d3c9ee0 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
@@ -1,4 +1,4 @@
-`include "./SRC/fpga_top.v"
+`include "./SRC/fpga_core.v"
 `include "./SRC/submodules/cbx_1__0_.v"
 `include "./SRC/submodules/cbx_1__0__old.v"
 `include "./SRC/submodules/cbx_1__1_.v"
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_core.v
similarity index 99%
rename from SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_core.v
index e86a40a..25e4e50 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_core.v
@@ -1,6 +1,6 @@
 //Generated from netlist by SpyDrNet
 //netlist name: FPGA88_SOFA_A
-module fpga_top
+module fpga_core
 (
     ccff_head,
     clk,
diff --git a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt
index dfb6622..bad5349 100644
--- a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt
+++ b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/shaping.txt
@@ -81,4 +81,4 @@
      tile_9__7_           right_tile         2154.18    2072.64   rect     4    0.000  0.000  0.000  383.520  361.100  383.520  361.100  0.000
      tile_9__8_           right_tile         2154.18    2458.88   rect     4    0.000  0.000  0.000  383.520  361.100  383.520  361.100  0.000
      tile_9__9_         top_right_tile       2154.18    2845.12   rect     4    0.000  0.000  0.000  484.160  361.100  484.160  361.100  0.000
-      fpga_top             fpga_top             0.00       0.00   rect     4    0.000  0.000  0.000  3334.720  2524.480  3334.720  2524.480  0.000
+     fpga_core            fpga_core             0.00       0.00   rect     4    0.000  0.000  0.000  3334.720  2524.480  3334.720  2524.480  0.000
diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_floorplan.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_floorplan.svg
index eeb94ae..031830c 100644
--- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_floorplan.svg
+++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_floorplan.svg
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="utf-8" ?>
 <svg xmlns="http://www.w3.org/2000/svg" xmlns:ev="http://www.w3.org/2001/xml-events" xmlns:xlink="http://www.w3.org/1999/xlink" baseProfile="full" height="100%" version="1.1" viewBox="-50,-333572,252548,333572" width="100%">
     <defs>
-        <symbol id="fpga_top">
-            <rect class="module_boundary fpga_top" fill="url(#id3)" height="333471" width="252447" x="1" y="1"/>
+        <symbol id="fpga_core">
+            <rect class="module_boundary fpga_core" fill="url(#id3)" height="333471" width="252447" x="1" y="1"/>
         </symbol>
         <symbol id="bottom_left_tile">
             <rect class="module_boundary bottom_left_tile" fill="#f4f0e6" height="13327" width="15455" x="1" y="1"/>
@@ -79,7 +79,7 @@
     </g>
     <g id="mainframe">
         <g id="mainShapes" transform="scale(1,-1)">
-            <use class="topModule" x="0" xlink:href="#fpga_top" y="0"/>
+            <use class="topModule" x="0" xlink:href="#fpga_core" y="0"/>
             <use class="tile_1__1_" x="920" xlink:href="#bottom_left_tile" y="544"/>
             <use class="tile_1__2_" x="920" xlink:href="#left_tile" y="14144"/>
             <use class="tile_1__3_" x="920" xlink:href="#left_tile" y="52768"/>
@@ -163,7 +163,7 @@
             <use class="tile_9__9_" x="215418" xlink:href="#top_right_tile" y="284512"/>
         </g>
         <g id="mainText" transform="scale(1,-1)">
-            <text alignment-baseline="middle" fill="black" text-anchor="middle" transform="scale(1,-1)" x="126224.0" y="-33347.200000000004">fpga_top</text>
+            <text alignment-baseline="middle" fill="black" text-anchor="middle" transform="scale(1,-1)" x="126224.0" y="-33347.200000000004">fpga_core</text>
             <text alignment-baseline="middle" fill="black" text-anchor="middle" transform="scale(1,-1)" x="8648.0" y="-7208.0">
                 tile_1__1_
                 <tspan dy="1.2em" x="8648.0" y="-7208.0">[bottom_left_tile]</tspan>