From 630c4060a8edecae424e926fa78e4bf41e95c422 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Nov 2020 15:12:00 -0700
Subject: [PATCH 1/3] [Arch] Detect some bugs (will not cause verification
 failed) in vpr arch

---
 ...ble_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index bf49476..8e19984 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -579,6 +579,10 @@
         <!-- We use direct connections to reduce the area to the most
              The global local routing is going to compensate the loss in routability
           -->
+        <!-- FIXME: The implicit port definition results in I0[0] connected to
+                    in[2]. Such twisted connection is not expected.
+                    I[0] should be connected to in[0]
+          -->
         <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>

From 1b2cf27c2af6bad30448adae0c57a6fa79cff830 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Nov 2020 15:12:32 -0700
Subject: [PATCH 2/3] [Testbench] Update post-PnR testbench with latest PnRed
 netlists

---
 .../verilog_testbench/and2_post_pnr_include_netlists.v    | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v
index 6903652..0bc9cc0 100644
--- a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -41,6 +41,14 @@
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
 
 // ------ Include fabric top-level netlists -----
 `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"

From 16af5e6ad82e73e4c6f96ab728d4b3002565d822 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Nov 2020 15:52:46 -0700
Subject: [PATCH 3/3] [Arch] Minor change to keep a regular arch in fle->lut
 connection

---
 ...scan_chain_nonLR_caravel_io_skywater130nm.xml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 8e19984..84c5991 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -583,49 +583,49 @@
                     in[2]. Such twisted connection is not expected.
                     I[0] should be connected to in[0]
           -->
-        <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
+        <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle1" input="clb.I1" output="fle[1:1].in[0:2]">
+        <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle2" input="clb.I2" output="fle[2:2].in[0:2]">
+        <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle3" input="clb.I3" output="fle[3:3].in[0:2]">
+        <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle4" input="clb.I4" output="fle[4:4].in[0:2]">
+        <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle5" input="clb.I5" output="fle[5:5].in[0:2]">
+        <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle6" input="clb.I6" output="fle[6:6].in[0:2]">
+        <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle7" input="clb.I7" output="fle[7:7].in[0:2]">
+        <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">