From aa845d506e2afd8c711b7f6b4bbee14da995d73d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Apr 2021 11:50:53 -0600 Subject: [PATCH] [Doc] Add introduction to the frontpage readme --- README.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 0b3b748..392e865 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,13 @@ ## Introduction -SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework +SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework. + +This repository provide the following support for the eFPGA IPs +- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project(https://github.com/lnis-uofu/OpenFPGA)]. +- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications +- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs +- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details