diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga index f6c4a35..85b4205 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga @@ -25,21 +25,21 @@ build_fabric --compress_routing #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt --depth 1 +write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1 # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist # which is required by Synopsys ICC2 parser -write_fabric_verilog --file ./SRC \ +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \ --explicit_port_mapping \ --verbose # Write the SDC files for PnR backend # - Turn on every options here -write_pnr_sdc --file ./SDC +write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} # Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc +write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc # Finish and exit OpenFPGA exit diff --git a/SCRIPT/openfpga_task/k4_cc_fdms/device_2x2/generate_fabric/config/task.conf b/SCRIPT/openfpga_task/k4_cc_fdms/device_2x2/generate_fabric/config/task.conf index d1556eb..73ff84d 100644 --- a/SCRIPT/openfpga_task/k4_cc_fdms/device_2x2/generate_fabric/config/task.conf +++ b/SCRIPT/openfpga_task/k4_cc_fdms/device_2x2/generate_fabric/config/task.conf @@ -16,14 +16,16 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_ROOT}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_ROOT}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdms_cc [ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_ROOT}/ARCH/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v