From 9dc1b6efa73563540e1c7af530fad73f751e5489 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Dec 2020 11:25:07 -0700 Subject: [PATCH] [Doc] Fine tune documentation on I/O design --- DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst index 3ef3230..7f3105a 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst @@ -21,7 +21,7 @@ As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in - An internal configurable memory element to control the direction of I/O cell -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where +The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC (which requires an active-low signal to enable output directionality), where - When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode