From 9caffc11d208f84ef0a34b1f93fbc87cccd146ae Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 1 Mar 2023 10:09:45 -0700 Subject: [PATCH] Added global signal connectivity patterns --- .../generate_global_signals_connectivity.py | 93 ++ SOFA_A/CommonFiles/render_sofa_a.py | 8 + SOFA_A/FPGA88_SOFA_A/config.sh | 1 + .../svg/FPGA88_SOFA_A_restruct_render.svg | 64 -- .../release/svg/config_enable_pattern.svg | 854 ++++++++++++++++++ .../release/svg/prog_reset_pattern.svg | 854 ++++++++++++++++++ .../release/svg/reset_pattern.svg | 854 ++++++++++++++++++ .../release/svg/test_enable_pattern.svg | 854 ++++++++++++++++++ 8 files changed, 3518 insertions(+), 64 deletions(-) create mode 100644 SOFA_A/CommonFiles/generate_global_signals_connectivity.py create mode 100644 SOFA_A/FPGA88_SOFA_A/release/svg/config_enable_pattern.svg create mode 100644 SOFA_A/FPGA88_SOFA_A/release/svg/prog_reset_pattern.svg create mode 100644 SOFA_A/FPGA88_SOFA_A/release/svg/reset_pattern.svg create mode 100644 SOFA_A/FPGA88_SOFA_A/release/svg/test_enable_pattern.svg diff --git a/SOFA_A/CommonFiles/generate_global_signals_connectivity.py b/SOFA_A/CommonFiles/generate_global_signals_connectivity.py new file mode 100644 index 0000000..bb3cc9c --- /dev/null +++ b/SOFA_A/CommonFiles/generate_global_signals_connectivity.py @@ -0,0 +1,93 @@ +""" +This file creates the feedthroughs for the global signals + +""" + + +import os +import pickle +from pathlib import Path +from svgwrite.container import Group +from spydrnet_physical.util import ConnectionPattern + +PROJ_NAME = os.environ["PROJ_NAME"] +RELEASE_DIR = os.environ["RELEASE_DIRECTORY"] +FPGA_SIZE_X = int(os.environ["FPGA_SIZE_X"]) +FPGA_SIZE_Y = int(os.environ["FPGA_SIZE_Y"]) +SVG_DIR = f"{RELEASE_DIR}/svg" +PICKLE_DIR = f"{RELEASE_DIR}/pickle/" + + +def save_svg_with_background(svg, filename, show_markers=False): + """ + Saves image with background image + """ + dwg = pickle.load( + open(f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen_pre_tile_grid.pickle", "rb")).dwg + scalex, scaley = 1.02, 1.02 + tx, ty = -7.5, -7.3 + tx, ty = 5.2, 5.2 + # Add main group + main_group = [e for e in svg.elements if e.get_id() == "main"][0] + main_group["transform"] = f"scale({scalex},-{scaley}) translate({tx}, {ty})" + dwg.add(main_group) + # Add marker + if show_markers: + markers = {ele["id"]: ele for ele in svg.elements if isinstance(ele, Group)}[ + "markers" + ] + markers["transform"] = f"scale({scalex},-{scaley}) translate({tx}, {ty})" + dwg.add(markers) + dwg.elements.extend(svg.defs.elements) + dwg.defs.add(dwg.style(r".connection{stroke-width:0.6 !important;}")) + dwg.saveas(f"{SVG_DIR}/{filename}", pretty=True, indent=4) + print(f"Saving {SVG_DIR}/{filename}") + + +def main(): + """ + Main method to generate connection patterns + """ + GRID_W = FPGA_SIZE_X + GRID_H = FPGA_SIZE_Y + + # ========================================================================== + # reset and test_enable connection + # ========================================================================== + p_manager = ConnectionPattern(GRID_W, GRID_H) + fishbone_pattern = p_manager.get_fishbone( + GRID_H+1, GRID_W, steps=1, x_margin=(0, 1)) + fishbone_pattern.make_top_connection(fishbone_pattern.points[0]) + fishbone_pattern.translate(0, 0) + fishbone_pattern.rotate(90) + + svg = p_manager.render_pattern(scale=13.8) + save_svg_with_background(svg, "reset_pattern.svg", show_markers=True) + save_svg_with_background(svg, "test_enable_pattern.svg", show_markers=True) + with open(PICKLE_DIR+"reset_pattern.pickle", 'wb') as file_ptr: + pickle.dump(fishbone_pattern, file_ptr) + with open(PICKLE_DIR+"test_enable_pattern.pickle", 'wb') as file_ptr: + pickle.dump(fishbone_pattern, file_ptr) + + # ========================================================================== + # prog_reset and config_enable connection + # ========================================================================== + p_manager = ConnectionPattern(GRID_W, GRID_H) + fishbone_pattern = p_manager.get_fishbone(GRID_H, GRID_W, steps=1) + fishbone_pattern.make_top_connection(fishbone_pattern.points[0]) + fishbone_pattern.rotate(270) + + svg = p_manager.render_pattern(scale=13.8) + save_svg_with_background(svg, "prog_reset_pattern.svg", show_markers=True) + save_svg_with_background( + svg, "config_enable_pattern.svg", show_markers=True) + with open(PICKLE_DIR+"prog_reset_pattern.pickle", 'wb') as file_ptr: + pickle.dump(fishbone_pattern, file_ptr) + with open(PICKLE_DIR+"config_enable_pattern.pickle", 'wb') as file_ptr: + pickle.dump(fishbone_pattern, file_ptr) + + +if __name__ == "__main__": + Path(SVG_DIR).mkdir(parents=True, exist_ok=True) + Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True) + main() diff --git a/SOFA_A/CommonFiles/render_sofa_a.py b/SOFA_A/CommonFiles/render_sofa_a.py index 7c45695..560cd69 100644 --- a/SOFA_A/CommonFiles/render_sofa_a.py +++ b/SOFA_A/CommonFiles/render_sofa_a.py @@ -47,9 +47,17 @@ def main(): dwg = fpga.render_layout( filename=f"{SVG_DIR}/{PROJ_NAME}_render.svg", grid_io=True) + dwg.save(pretty=True, indent=4) + pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb")) dwg.save(pretty=True, indent=4) pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb")) logger.info("Saving file %s/%s_render.svg", SVG_DIR, PROJ_NAME) + pickle.dump(fpga, open( + f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen_pre_tile_grid.pickle", "wb")) + + dwg = fpga.render_layout(filename="_tmp.svg", grid_io=False) + pickle.dump(fpga, open( + f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen_pre_tile.pickle", "wb")) # ============ Modify your floorplan here ============ # Adding stylesheet diff --git a/SOFA_A/FPGA88_SOFA_A/config.sh b/SOFA_A/FPGA88_SOFA_A/config.sh index f7ee0ca..1b17572 100644 --- a/SOFA_A/FPGA88_SOFA_A/config.sh +++ b/SOFA_A/FPGA88_SOFA_A/config.sh @@ -17,6 +17,7 @@ export_ GENERATE_FABRIC_KEY = "../CommonFiles/render_sofa_a_fabric_key.py" export_ NETLIST_SYNTH_SCRIPT = "../CommonFiles/sofa_netlist_synth_script.sh" export_ RESTRUCT_NETLIST = "../CommonFiles/restructure_fabric_sofa_a.py" export_ CUSTOM_MODULES_LIST = "./${TASK_DIR_NAME}/CustomModules/custom_module.txt" +export_ GLOBAL_FT_SCRIPT = "../CommonFiles/generate_global_signals_connectivity.py" # Complete Chip (fpga_top) or eFPGA (fpga_core) export_ DESIGN_NAME = fpga_core diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_restruct_render.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_restruct_render.svg index 4f6a064..d00b906 100644 --- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_restruct_render.svg +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_restruct_render.svg @@ -279,14 +279,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - - - - - - - @@ -304,7 +296,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -322,7 +313,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -340,7 +330,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -358,7 +347,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -376,7 +364,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -394,7 +381,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -412,7 +398,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -430,7 +415,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -448,7 +432,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -466,7 +449,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -484,7 +466,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -502,7 +483,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -520,7 +500,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -538,7 +517,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -556,7 +534,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -574,7 +551,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - @@ -592,14 +568,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - - - - - - - - @@ -666,14 +634,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} - io_left_0__1_ - io_left_0__2_ - io_left_0__3_ - io_left_0__4_ - io_left_0__5_ - io_left_0__6_ - io_left_0__7_ - io_left_0__8_ sb_0__0_ cby_0__1_ sb_0__1_ @@ -691,7 +651,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_0__7_ cby_0__8_ sb_0__8_ - io_bottom_1__0_ cbx_1__0_ clb_1__1_ cbx_1__1_ @@ -709,7 +668,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_1__7_ clb_1__8_ cbx_1__8_ - io_top_1__9_ sb_1__0_ cby_1__1_ sb_1__1_ @@ -727,7 +685,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_1__7_ cby_1__8_ sb_1__8_ - io_bottom_2__0_ cbx_2__0_ clb_2__1_ cbx_2__1_ @@ -745,7 +702,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_2__7_ clb_2__8_ cbx_2__8_ - io_top_2__9_ sb_2__0_ cby_2__1_ sb_2__1_ @@ -763,7 +719,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_2__7_ cby_2__8_ sb_2__8_ - io_bottom_3__0_ cbx_3__0_ clb_3__1_ cbx_3__1_ @@ -781,7 +736,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_3__7_ clb_3__8_ cbx_3__8_ - io_top_3__9_ sb_3__0_ cby_3__1_ sb_3__1_ @@ -799,7 +753,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_3__7_ cby_3__8_ sb_3__8_ - io_bottom_4__0_ cbx_4__0_ clb_4__1_ cbx_4__1_ @@ -817,7 +770,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_4__7_ clb_4__8_ cbx_4__8_ - io_top_4__9_ sb_4__0_ cby_4__1_ sb_4__1_ @@ -835,7 +787,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_4__7_ cby_4__8_ sb_4__8_ - io_bottom_5__0_ cbx_5__0_ clb_5__1_ cbx_5__1_ @@ -853,7 +804,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_5__7_ clb_5__8_ cbx_5__8_ - io_top_5__9_ sb_5__0_ cby_5__1_ sb_5__1_ @@ -871,7 +821,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_5__7_ cby_5__8_ sb_5__8_ - io_bottom_6__0_ cbx_6__0_ clb_6__1_ cbx_6__1_ @@ -889,7 +838,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_6__7_ clb_6__8_ cbx_6__8_ - io_top_6__9_ sb_6__0_ cby_6__1_ sb_6__1_ @@ -907,7 +855,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_6__7_ cby_6__8_ sb_6__8_ - io_bottom_7__0_ cbx_7__0_ clb_7__1_ cbx_7__1_ @@ -925,7 +872,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_7__7_ clb_7__8_ cbx_7__8_ - io_top_7__9_ sb_7__0_ cby_7__1_ sb_7__1_ @@ -943,7 +889,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_7__7_ cby_7__8_ sb_7__8_ - io_bottom_8__0_ cbx_8__0_ clb_8__1_ cbx_8__1_ @@ -961,7 +906,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} cbx_8__7_ clb_8__8_ cbx_8__8_ - io_top_8__9_ sb_8__0_ cby_8__1_ sb_8__1_ @@ -979,14 +923,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;} sb_8__7_ cby_8__8_ sb_8__8_ - io_right_9__1_ - io_right_9__2_ - io_right_9__3_ - io_right_9__4_ - io_right_9__5_ - io_right_9__6_ - io_right_9__7_ - io_right_9__8_ diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/config_enable_pattern.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/config_enable_pattern.svg new file mode 100644 index 0000000..bf18a50 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/release/svg/config_enable_pattern.svg @@ -0,0 +1,854 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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