Merge branch 'master' into arch_exploration

2021-04-05 08:52:14 -06:00 · 2021-04-05 08:52:14 -06:00 · 9ba10b3700
parent 2fc7cf5b71 2332e79e90
commit 9ba10b3700
38 changed files with 3960 additions and 192 deletions
--- a/.github/workflows/buildDocker.yml
+++ b/.github/workflows/buildDocker.yml
@ -0,0 +1,50 @@
+# ##############################################################################
+# TODO: Add verification task after the netlist modification
+################################################################################
+
+name: Arch XML Regression
+
+# Run CI on push on each branch
+on:
+  push:
+  pull_request:
+
+jobs:
+  generate_netlist:
+    name: Arch development
+    runs-on: ubuntu-18.04
+    container: ghcr.io/lnis-uofu/openfpga-master:latest
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+          - name: "FPGA1212_QLSOFA_HD"
+          - name: "FPGA1212_SOFA_CHD"
+          - name: "FPGA1212_SOFA_HD"
+    steps:
+      - name: Runner workspace path
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+      - name: Checkout OpenFPGA-ArcticPro3 repo
+        uses: actions/checkout@v2
+      - name: Detect changes
+        uses: technote-space/get-diff-action@v4
+        with:
+          PATTERNS: |
+            ${{ matrix.config.name }}_PNR/*_task/**
+      - name: Running benchmark
+        shell: bash
+        if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') }}
+        run: |
+          ${PYTHON_EXEC} -m pip install -r requirements.txt
+          cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
+          cd ${{ matrix.config.name }}_PNR && make clean runOpenFPGA
+      - name: Upload artifact
+        uses: actions/upload-artifact@v2
+        if: ${{ failure() }}
+        with:
+          name: failed_${{matrix.config.name}}_regression_log
+          retention-days: 1
+          path: "${{ matrix.config.name }}_PNR/*_task/latest/*.log"
--- a/.github/workflows/perform_precheck.sh
+++ b/.github/workflows/perform_precheck.sh
@ -8,6 +8,13 @@ cd ./${DEST_DIR}
 echo "[Info] Running in directory ${PWD}"

 cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
+if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
+    sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
+    status=$?
+    [ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
+fi
+fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
+
 make uncompress
 echo "[Info] All files are uncompressed"

@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
    /usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
    echo "[Info] Create compare_caravel.txt"
 fi
+echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1
--- a/.gitignore
+++ b/.gitignore
@ -11,3 +11,4 @@
 **/SRC**/*_tb.v
 **/SDC/**/*.sdc
 !**/SDC/**/disable_configure_ports.sdc
+*/runOpenFPGA
--- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
-LUT3_DELAY: 2.31e-9
-LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
-LUT4_DELAY: 2.6e-9
-LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT3_DELAY: 0.86e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.14e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
 REGIN_TO_FF0_DELAY: 0.58e-9
 FF0_TO_FF1_DELAY: 0.56e-9
--- a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
@ -1,7 +1,7 @@
-L1_SB_MUX_DELAY: 1.44e-9
-L2_SB_MUX_DELAY: 1.44e-9
-L4_SB_MUX_DELAY: 1.44e-9
-CB_MUX_DELAY: 1.38e-9
+L1_SB_MUX_DELAY: 0.81e-9
+L2_SB_MUX_DELAY: 0.81e-9
+L4_SB_MUX_DELAY: 0.81e-9
+CB_MUX_DELAY: 0.57e-9
 L1_WIRE_R: 100
 L1_WIRE_C: 1e-12
 L2_WIRE_R: 100
@ -12,15 +12,15 @@ INPAD_DELAY: 0.11e-9
 OUTPAD_DELAY: 0.11e-9
 FF_T_SETUP: 0.39e-9
 FF_T_CLK2Q: 0.43e-9
-LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
-LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
-LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
-FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
-LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
-FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
-LUT3_DELAY: 2.31e-9
-LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
-LUT4_DELAY: 2.6e-9
-LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
-REGIN_TO_FF0_DELAY: 1.12e-9
-FF0_TO_FF1_DELAY: 0.56e-9
+LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
+LUT3_DELAY: 0.86e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
+LUT4_DELAY: 1.20e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
+REGIN_TO_FF0_DELAY: 0.15e-9
+FF0_TO_FF1_DELAY: 0.16e-9
--- a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
-LUT3_DELAY: 2.31e-9
-LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
-LUT4_DELAY: 2.6e-9
-LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
+LUT3_DELAY: 0.92e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.21e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
 REGIN_TO_FF0_DELAY: 1.12e-9
 FF0_TO_FF1_DELAY: 0.56e-9
--- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg
+++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg
@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
-<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" xmlns:dc="http://purl.org/dc/elements/1.1/" version="1.1" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
+<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
  <defs>
    <font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
      <font-face-src>
@ -23,8 +23,8 @@
      </font-face-src>
    </font-face>
  </defs>
-  <metadata> Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000</metadata>
-  <g id="schematic_timing" stroke-dasharray="none" fill-opacity="1" stroke-opacity="1" fill="none" stroke="none">
+  <metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
+  <g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
    <title>schematic_timing</title>
    <g id="schematic_timing_图层_1">
      <title>图层 1</title>
@ -392,6 +392,11 @@
          <tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
        </text>
      </g>
+      <g id="Graphic_266">
+        <text transform="translate(223.72933 316.22945)" fill="#ff2600">
+          <tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
+        </text>
+      </g>
    </g>
  </g>
 </svg>
--- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst
+++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst
@ -8,12 +8,12 @@ Timing Annotation
 Configurable Logic Block
 ^^^^^^^^^^^^^^^^^^^^^^^^

-The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
+The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.

 .. _fig_qlsofa_hd_fle_arch_timing:

 .. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
-  :scale: 30%
+  :width: 80%
  :alt: Schematic of a logic element used in QLSOFA HD FPGA

  Schematic of a logic element used in QLSOFA HD FPGA
@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
  +-------------------------+------------------------------+
  | Path / Delay            | TT (unit: ns)                |
  +=========================+==============================+
-  | in0 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[0]      | 0.85                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[0]      | 0.57                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in2 -> B                | 0.60                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT3_out[1] [1]_ | 2.31                         |
+  |   B -> LUT3_out[0]      | 0.32                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[1]      | 0.90                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[1]      | 0.62                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT4_out [1]_    | 2.60                         |
+  |   B -> LUT3_out[1]      | 0.33                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT4_out [1]_    | 2.60                         |
+  | in0 -> LUT4_out         | 1.17                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT4_out [1]_    | 2.60                         |
+  | in1 -> LUT4_out         | 0.89                         |
  +-------------------------+------------------------------+
-  | in3 -> LUT4_out [1]_    | 2.60                         |
+  | in2 -> LUT4_out         | 1.21                         |
+  +-------------------------+------------------------------+
+  | in3 -> LUT4_out         | 0.79                         |
  +-------------------------+------------------------------+
  | LUT3_out[0] -> A        | 0.56                         |
  +-------------------------+------------------------------+
@ -66,8 +68,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
  | FF[0] -> FF[1]          | 0.56                         |
  +-------------------------+------------------------------+

-.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
-
 .. _qlsofa_hd_timing_io:

 I/O Block
--- a/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX2_1.pdf
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX2_1.pdf
--- a/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX3_1.pdf
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX3_1.pdf
--- a/DOC/source/datasheet/sofa_chd/custom_cells/custom_cells.rst
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/custom_cells.rst
@ -0,0 +1,133 @@
+=========================================================
+Skywater Custom Multiplexer Cells
+=========================================================
+
+
+Background
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Traditionally, larger multiplexers are built using trees of smaller multiplexers as illustrated below:
+
+.. image:: figures/mux_tree.png
+    :align: center
+    :alt: Traditional Multiplexer Tree
+
+Multiplexers trees lead to large power and timing constraints that limit FPGA performance. FPGA fabrics use complementary pass gate logic (CPL) to replace multiplexer trees with single level inverted transmission gate derived multiplexers, as illustrated below:
+
+.. image:: figures/fpga_mux.png
+    :height: 400px
+    :width: 800px
+    :align: center
+    :alt: Single Level FPGA Multiplexer
+
+Single level multiplexers are controlled through configuration SRAM cells which enable high impedance connections throughout the multiplexer hierarchy, thereby removing the need for hierarchical designs of multiplexers.  Therefore, the CPL multiplexers enable increased performance and reduced power consumption throughout FPGA fabrics. Standard cells required for CPL multiplexers are not commonly included in PDKs, thereby requiring the need for custom cell creation to enable FPGA multiplexer hierarchies. The remainder of this document is dedicated to the architecture and performance evaluation of our *sky130_uuopenfpga_cc_hd_invmux2_1*/*sky130_uuopenfpga_cc_hd_invmux3_1* custom cells generated using the Skywater 130nm PDK. A comparison is achieved by generating 4-to-1 multiplexer and 6-to-1 multiplexers made from our cells and standard cells provided within the Skywater 130nm PDK.
+
+.. INVMUX2_1
+
+SKY130_UUOPENFPGA_CC_HD_INVMUX2_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Usage: 2-Input Transmission Gate Multiplexer with Unity Drive Strength Inverter Input
+    -Pins: 
+        - Q1/Q2 - Inverter Input
+        - S0/S1 - NMOS Select Input
+        - S0B/S1B - PMOS Select Input
+
+- Schematic:
+
+.. image:: figures/sky130_fd_sc_hd_mux2_1\ schematic.png
+    :height: 400px
+    :width: 500px
+    :align: center
+    :alt: Sky130_uuopenfpga_cc_hd_invmux2_1 Schematic
+
+- Layout:\
+
+.. image:: figures/sky130_fd_sc_hd_mux2_1\ gds.png
+    :height: 450px
+    :width: 800px
+    :align: center
+    :alt: Sky130_uuopenfpga_cc_hd_invmux2_1 Layout
+
+- Comparison: To demonstrate the performance gains using CPL multiplexers, we built a 4-1 single level multiplexer using our custom *sky130_uuopenfpga_cc_hd_invmux2_1* cell along with a 4-to-1 multiplexer using the *sky130_fd_sc_hd__mux2_1* as the root cell of the multiplexer tree.
+
+The *sky130_fd_sc_hd_mux2_1* multiplexer is built using a static CMOS structure with a single select input, whereas our cell uses a fractured select hierarchy. To perform the comparisons we have tabulated values in regards to power, area, and timing for the 4-to-1 multiplexer tree using Cadence ADE XL.
+
+- Power:
+      - sky130_uuopenfpga_cc_hd_invmux2_1:  2.37 μW
+      - sky130_fd_sc_hd__mux2_1:            3.03 μW
+
+Our custom multiplexer provides a 22\% reduction in power consumption.
+
+- Area:
+    - sky130_uuopenfpga_cc_hd_invmux2_1:    33.78 μA\ :sup:`2`
+    - sky130_fd_sc_hd__mux2_1:              33.78 μA\ :sup:`2`
+  
+Our multiplexer implementation requires equal area neglecting interconnect overhead.
+
+- Timing:
+    - sky130_uuopenfpga_cc_hd_invmux2_1:    211.1 ps
+    - sky130_fd_sc_hd__mux2_1:              304.3 ps
+
+Our custom multiplexer provides over a 31\% reduction in propagation delay.
+
+`SKY130_UUOPENFPGA_CC_HD_INVMUX2_1 Cell Characterization`_
+
+.. _`SKY130_UUOPENFPGA_CC_HD_INVMUX2_1 Cell Characterization`: https://github.com/GrantBrown1994/SOFA/blob/documentation/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX2_1.pdf
+
+.. INVMUX2_1
+
+.. INVMUX3_1
+
+SKY130_UUOPENFPGA_CC_HD_INVMUX3_1
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Usage: 3-Input Transmission Gate Multiplexer with Unity Drive Strength Inverter Input
+    - Pins:
+        - Q2/Q3 - Inverted Input
+        - S0/S1/S2 - NMOS Select Input
+        - S0B/S1B/S2B - PMOS Select Input
+
+- Schematic:
+
+.. image:: figures/sky130_fd_sc_hd_mux3_1\ schematic.png
+    :height: 600px
+    :width: 600px
+    :align: center
+    :alt: Sky130_uuopenfpga_cc_hd_invmux3_1 Schematic
+
+- Layout:
+
+.. image:: figures/sky130_fd_sc_hd_mux3_1\ gds.png
+    :height: 400px
+    :width: 1100px
+    :align: center
+    :alt: Sky130_uuopenfpga_cc_hd_invmux3_1 Layout
+
+- Comparison: To demonstrate the performance gains using CPL multiplexers, we built a 6-1 single level multiplexer using our custom *sky130_uuopenfpga_cc_hd_invmux3_1* cell along with a 6-to-1 multiplexer using the *sky130_fd_sc_hd__mux4/2_1* as the root cells of the multiplexer tree.
+
+To perform the comparisons we have tabulated values in regards to power, area, and timing for the 4-to-1 multiplexer tree using Cadence ADE XL.
+
+- Power:
+      - sky130_uuopenfpga_cc_hd_invmux3_1:  2.96 μW
+      - sky130_fd_sc_hd__mux2_1:            3.31 μW
+  
+Our custom multiplexer provides a 10.5\% reduction in power consumption.
+
+- Area:
+    - sky130_uuopenfpga_cc_hd_invmux3_1:    61.31 μA\ :sup:`2`
+    - sky130_fd_sc_hd__mux2_1:              48.80 μA\ :sup:`2`
+
+The Skywater multiplexer provides a 20\% reduction in area.
+
+- Timing:
+    - sky130_uuopenfpga_cc_hd_invmux3_1:    272.6 ps
+    - sky130_fd_sc_hd__mux2_1:              374.2 ps
+
+Our custom multiplexer provides over a 27\% reduction in propagation delay.
+
+`SKY130_UUOPENFPGA_CC_HD_INVMUX3_1 Cell Characterization`_
+
+.. _`SKY130_UUOPENFPGA_CC_HD_INVMUX3_1 Cell Characterization`: https://github.com/GrantBrown1994/SOFA/blob/documentation/DOC/source/datasheet/sofa_chd/custom_cells/cell_eval/SKY130_UUOPENFPGA_CC_HD_INVMUX3_1.pdf
+
+.. INVMUX3_1
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/fpga_mux.png
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/fpga_mux.png
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/mux_tree.png
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/mux_tree.png
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux2_1
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux2_1
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux2_1
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux2_1
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux3_1
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux3_1
--- a/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux3_1
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/figures/sky130_fd_sc_hd_mux3_1
--- a/DOC/source/datasheet/sofa_chd/custom_cells/index.rst
+++ b/DOC/source/datasheet/sofa_chd/custom_cells/index.rst
@ -0,0 +1,10 @@
+.. _custom_cells:
+   Custom Cells
+
+Custom Cells
+--------
+ 
+.. toctree::
+   :maxdepth: 2
+
+   custom_cells
--- a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg
+++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg
@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
-<svg xmlns:xl="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" xmlns:dc="http://purl.org/dc/elements/1.1/" version="1.1" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
+<svg version="1.1" xmlns:xl="http://www.w3.org/1999/xlink" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://www.w3.org/2000/svg" viewBox="130.62533 187.22044 463.9655 252.71838" width="463.9655" height="252.71838">
  <defs>
    <font-face font-family="Times New Roman" font-size="15" panose-1="2 2 8 3 7 5 5 2 3 4" units-per-em="1000" underline-position="-108.88672" underline-thickness="95.21484" slope="0" x-height="456.54297" cap-height="662.1094" ascent="891.1133" descent="-216.3086" font-weight="700">
      <font-face-src>
@ -23,8 +23,8 @@
      </font-face-src>
    </font-face>
  </defs>
-  <metadata> Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000</metadata>
-  <g id="schematic_timing" stroke-dasharray="none" fill-opacity="1" stroke-opacity="1" fill="none" stroke="none">
+  <metadata> Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000</metadata>
+  <g id="schematic_timing" stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1">
    <title>schematic_timing</title>
    <g id="schematic_timing_图层_1">
      <title>图层 1</title>
@ -392,6 +392,11 @@
          <tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">A</tspan>
        </text>
      </g>
+      <g id="Graphic_266">
+        <text transform="translate(223.72933 316.22945)" fill="#ff2600">
+          <tspan font-family="Times New Roman" font-size="15" font-style="italic" font-weight="700" fill="#ff2600" x="0" y="13">B</tspan>
+        </text>
+      </g>
    </g>
  </g>
 </svg>
--- a/DOC/source/datasheet/sofa_chd/index.rst
+++ b/DOC/source/datasheet/sofa_chd/index.rst
@ -16,3 +16,5 @@ SOFA CHD
   sofa_chd_circuit_design

   sofa_chd_timing
+
+   custom_cells/index
--- a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst
+++ b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst
@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
 .. _fig_sofa_chd_fle_arch_timing:

 .. figure:: ./figures/sofa_chd_fle_arch_timing.svg
-  :scale: 30%
+  :width: 80%
  :alt: Schematic of a logic element used in SOFA CHD FPGA

  Schematic of a logic element used in SOFA CHD FPGA
@ -25,48 +25,49 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:
  +-------------------------+------------------------------+
  | Path / Delay            | TT (unit: ns)                |
  +=========================+==============================+
-  | in0 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[0]      | 0.86                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[0]      | 0.58                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in2 -> B                | 0.16                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT3_out[1] [1]_ | 2.31                         |
+  |   B -> LUT3_out[0]      | 0.32                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[1]      | 0.91                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[1]      | 0.63                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT4_out [1]_    | 2.60                         |
+  |   B -> LUT3_out[1]      | 0.34                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT4_out [1]_    | 2.60                         |
+  | in0 -> LUT4_out         | 1.20                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT4_out [1]_    | 2.60                         |
+  | in1 -> LUT4_out         | 0.92                         |
  +-------------------------+------------------------------+
-  | in3 -> LUT4_out [1]_    | 2.60                         |
+  | in2 -> LUT4_out         | 0.78                         |
  +-------------------------+------------------------------+
-  | LUT3_out[0] -> A        | 0.56                         |
+  | in3 -> LUT4_out         | 0.52                         |
  +-------------------------+------------------------------+
-  | LUT4_out[0] -> A        | 0.58                         |
+  | LUT3_out[0] -> A        | 0.17                         |
  +-------------------------+------------------------------+
-  | A -> out[0]             | 0.88                         |
+  | LUT4_out[0] -> A        | 0.18                         |
  +-------------------------+------------------------------+
-  | A -> FF[0]              | 0.56                         |
+  | A -> out[0]             | 0.48                         |
  +-------------------------+------------------------------+
-  | FF[0] -> out[0]         | 0.88                         |
+  | A -> FF[0]              | 0.15                         |
  +-------------------------+------------------------------+
-  | LUT3_out[1] -> out[1]   | 0.89                         |
+  | FF[0] -> out[0]         | 0.48                         |
  +-------------------------+------------------------------+
-  | LUT3_out[1] -> FF[1]    | 0.56                         |
+  | LUT3_out[1] -> out[1]   | 0.47                         |
  +-------------------------+------------------------------+
-  | FF[1] -> out[1]         | 0.89                         |
+  | LUT3_out[1] -> FF[1]    | 0.16                         |
  +-------------------------+------------------------------+
-  | regin -> FF[0]          | 0.58                         |
+  | FF[1] -> out[1]         | 0.37                         |
  +-------------------------+------------------------------+
-  | FF[0] -> FF[1]          | 0.56                         |
+  | regin -> FF[0]          | 0.15                         |
+  +-------------------------+------------------------------+
+  | FF[0] -> FF[1]          | 0.16                         |
  +-------------------------+------------------------------+

-.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.

 .. _sofa_chd_timing_io:

@ -89,12 +90,12 @@ The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`tab
  +---------------------------+------------------------------+
  | Path / Delay              | TT (unit: ns)                |
  +===========================+==============================+
-  | A -> B                    | 1.44                         |
+  | A -> B                    | 0.81                         |
  +---------------------------+------------------------------+
-  | A -> C                    | 1.44                         |
+  | A -> C                    | 0.81                         |
  +---------------------------+------------------------------+
-  | A -> D                    | 1.44                         |
+  | A -> D                    | 0.81                         |
  +---------------------------+------------------------------+
-  | B -> E                    | 1.38                         |
+  | B -> E                    | 0.57                         |
  +---------------------------+------------------------------+

--- a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst
+++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst
@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
 .. _fig_sofa_hd_fle_arch_timing:

 .. figure:: ./figures/sofa_hd_fle_arch_timing.svg
-  :scale: 30%
+  :width: 80%
  :alt: Schematic of a logic element used in SOFA HD FPGA

  Schematic of a logic element used in SOFA HD FPGA
@ -25,25 +25,25 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
  +-------------------------+------------------------------+
  | Path / Delay            | TT (unit: ns)                |
  +=========================+==============================+
-  | in0 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[0]      | 0.85                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[0]      | 0.57                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[0] [1]_ | 2.31                         |
+  | in2 -> LUT3_out[0]      | 0.30                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in0 -> LUT3_out[1]      | 0.86                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in1 -> LUT3_out[1]      | 0.59                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT3_out[1] [1]_ | 2.31                         |
+  | in2 -> LUT3_out[1]      | 0.31                         |
  +-------------------------+------------------------------+
-  | in0 -> LUT4_out [1]_    | 2.60                         |
+  | in0 -> LUT4_out         | 1.14                         |
  +-------------------------+------------------------------+
-  | in1 -> LUT4_out [1]_    | 2.60                         |
+  | in1 -> LUT4_out         | 0.86                         |
  +-------------------------+------------------------------+
-  | in2 -> LUT4_out [1]_    | 2.60                         |
+  | in2 -> LUT4_out         | 0.58                         |
  +-------------------------+------------------------------+
-  | in3 -> LUT4_out [1]_    | 2.60                         |
+  | in3 -> LUT4_out         | 0.51                         |
  +-------------------------+------------------------------+
  | LUT3_out[0] -> A        | 0.56                         |
  +-------------------------+------------------------------+
@ -66,8 +66,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`
  | FF[0] -> FF[1]          | 0.56                         |
  +-------------------------+------------------------------+

-.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
-
 .. _sofa_hd_timing_io:

 I/O Block
--- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
+++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
@ -13,21 +13,27 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
+arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
+
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
+openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
+external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60

 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
+arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml

 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
+bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif

 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
+bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
+bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v

 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 vpr_fpga_verilog_formal_verification_top_netlist=
--- a/FPGA1212_QLSOFA_HD_PNR/Makefile
+++ b/FPGA1212_QLSOFA_HD_PNR/Makefile
@ -0,0 +1,40 @@
+##########################################################################################
+##########################################################################################
+
+SHELL=bash
+PYTHON_EXEC=python3.8
+RERUN = 0
+TB = top
+OPTIONS =
+
+.SILENT:
+.ONESHELL:
+
+runOpenFPGA:
+	SECONDS=0
+	source config.sh
+	# =====================  Check Tools  =====================
+	which python3.8 > /dev/null
+	if [ $$? -eq 1 ]; then
+		echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
+	fi
+
+	# ===================  Clean Previous Run  =================================
+	rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
+	(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
+
+	# =====================  Generate Netlist  =================================
+	(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
+	run-task $${TASK_DIR_NAME} --remove_run_dir all
+	run-task $${TASK_DIR_NAME} ${OPTIONS})
+
+	if [ $$? -eq 1 ]; then
+		echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
+	fi
+
+	duration=$$SECONDS
+	date > runOpenFPGA
+	echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
+
+clean:
+	rm -rf runOpenFPGA
--- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf
+++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task_simulation.conf
@ -13,21 +13,27 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
+arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
+
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
+openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
+external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60

 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
+arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml

 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
+bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif

 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
+bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
+bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v

 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 vpr_fpga_verilog_formal_verification_top_netlist=
--- a/FPGA1212_SOFA_CHD_PNR/Makefile
+++ b/FPGA1212_SOFA_CHD_PNR/Makefile
@ -0,0 +1,40 @@
+##########################################################################################
+##########################################################################################
+
+SHELL=bash
+PYTHON_EXEC=python3.8
+RERUN = 0
+TB = top
+OPTIONS =
+
+.SILENT:
+.ONESHELL:
+
+runOpenFPGA:
+	SECONDS=0
+	source config.sh
+	# =====================  Check Tools  =====================
+	which python3.8 > /dev/null
+	if [ $$? -eq 1 ]; then
+		echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
+	fi
+
+	# ===================  Clean Previous Run  =================================
+	rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
+	(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
+
+	# =====================  Generate Netlist  =================================
+	(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
+	run-task $${TASK_DIR_NAME} --remove_run_dir all
+	run-task $${TASK_DIR_NAME} ${OPTIONS})
+
+	if [ $$? -eq 1 ]; then
+		echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
+	fi
+
+	duration=$$SECONDS
+	date > runOpenFPGA
+	echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
+
+clean:
+	rm -rf runOpenFPGA
--- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf
+++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf
@ -13,21 +13,27 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
+arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
+
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
+openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
+external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40

 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
+arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml

 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
+bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif

 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
+bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
+bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v

 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 vpr_fpga_verilog_formal_verification_top_netlist=
--- a/FPGA1212_SOFA_HD_PNR/Makefile
+++ b/FPGA1212_SOFA_HD_PNR/Makefile
@ -0,0 +1,40 @@
+##########################################################################################
+##########################################################################################
+
+SHELL=bash
+PYTHON_EXEC=python3.8
+RERUN = 0
+TB = top
+OPTIONS =
+
+.SILENT:
+.ONESHELL:
+
+runOpenFPGA:
+	SECONDS=0
+	source config.sh
+	# =====================  Check Tools  =====================
+	which python3.8 > /dev/null
+	if [ $$? -eq 1 ]; then
+		echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
+	fi
+
+	# ===================  Clean Previous Run  =================================
+	rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
+	(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
+
+	# =====================  Generate Netlist  =================================
+	(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
+	run-task $${TASK_DIR_NAME} --remove_run_dir all
+	run-task $${TASK_DIR_NAME} ${OPTIONS})
+
+	if [ $$? -eq 1 ]; then
+		echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
+	fi
+
+	duration=$$SECONDS
+	date > runOpenFPGA
+	echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
+
+clean:
+	rm -rf runOpenFPGA
--- a/LIB/sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib
+++ b/LIB/sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib
--- a/README.md
+++ b/README.md
@ -21,24 +21,47 @@ This repository provide the following support for the eFPGA IPs

 ## Quick Start

+To run the user flow using SOFA repository you need to have OpenFPGA installed.
+Please visit https://github.com/lnis-uofu/OpenFPGA#compilation for OpenFPGA installaton.
+
 ```bash
-#Clone the repository and go inside it
-git clone https://github.com/LNIS-Projects/skywater-openfpga.git
-python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
+export OPENFPGA_PATH=<path_to_openfpga_root>
+
+# Clone the SOFA repository
+git clone https://github.com/lnis-uofu/SOFA.git
+
+# ======== Goto specific design ========
+# FPGA1212_SOFA_CHD_PNR
+# FPGA1212_QLSOFA_HD_PNR
+# FPGA1212_SOFA_HD_PNR
+cd FPGA1212_QLSOFA_HD_PNR
+
+# ======== Run example OpenFPGA Task ========
+make runOpenFPGA
+
+# ======== To view the results ========
+cat FPGA1212_QLSOFA_HD_task/latest/task_result.csv
+
+# ======== To view detailed log ========
+cat codeopen FPGA1212_QLSOFA_HD_task/latest/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/**/openfpgashell.log
+
 ```
+### To bechmark your own design
+Copy your verilog file `FPGA1212_QLSOFA_HD_task/micro_benchmark` directory
+and modify `FPGA1212_QLSOFA_HD_task/config/task_simulation.conf` file.
+
+Details of different paramters can be found [Configure run_fpga_task](https://openfpga.readthedocs.io/en/latest/manual/openfpga_flow/run_fpga_task/)
+
+```bash
+cd FPGA1212_QLSOFA_HD_PNR
+vi FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
+```
+
 ---

-* If you have openfpga repository cloned at the same level of this project, you can simple call
-```bash
-  python3 SCRIPT/repo_setup.py
-``` 
-
-Otherwise, you should provide full path using the option _--openfpga\_root\_path_ 
-
-
 ## Chip Gallery

-You can find a chip gallery in the online documentation.
+You can find a chip gallery in the online documentation

 ## Directory Organization

--- a/SNPS_PT/SCRIPT/report_timing_cb.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl
@ -5,19 +5,23 @@
 #
 ##################################
 # Define environment variables
+#
+#set DEVICE_NAME "SOFA_HD"
+#set DEVICE_NAME "QLSOFA_HD"
+set DEVICE_NAME "SOFA_CHD"
+
 set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";

-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+if {"SOFA_HD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { 
  set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
-
-#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
-#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
-
-#set DEVICE_NAME "SOFA_HD"
-set DEVICE_NAME "QLSOFA_HD"
-#set DEVICE_NAME "SOFA_CHD"
+} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+}

 set TIMING_REPORT_HOME "../TIMING_REPORTS/";

@ -26,9 +30,13 @@ set_app_var svr_enable_vpp true
 # Enable reporting ALL the timing paths even those are NOT constrained
 set_app_var timing_report_unconstrained_paths true

+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
+  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
+} else {
  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
-
  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+}

 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
 
@ -45,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
  ##################################
  # Read timing libraries
  read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+  if {"SOFA_CHD" == ${DEVICE_NAME}} {
+    read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
+  }
  
  ##################################
  # Read post-PnR netlists
--- a/SNPS_PT/SCRIPT/report_timing_clb.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl
@ -5,19 +5,23 @@
 
 ##################################
 # Define environment variables
+#
+#set DEVICE_NAME "SOFA_HD"
+#set DEVICE_NAME "QLSOFA_HD"
+set DEVICE_NAME "SOFA_CHD"
+
 set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";

-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+if {"SOFA_HD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { 
  set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
-
-#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
-#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
-
-#set DEVICE_NAME "SOFA_HD"
-set DEVICE_NAME "QLSOFA_HD"
-#set DEVICE_NAME "SOFA_CHD"
+} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+}

 set TIMING_REPORT_HOME "../TIMING_REPORTS/";

@ -26,9 +30,13 @@ set_app_var svr_enable_vpp true
 # Enable reporting ALL the timing paths even those are NOT constrained
 set_app_var timing_report_unconstrained_paths tr

+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
+  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
+} else {
  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
-
  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+}

 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"

@ -40,6 +48,9 @@ remove_lib -all
 ##################################
 # Read timing libraries
 read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
+}

 ##################################
 # Read post-PnR netlists
@ -51,12 +62,16 @@ link_design ${DESIGN_NAME}

 #########################################
 # Setup constraints to break combinational loops
-if {${DEVICE_NAME} eq "SOFA_HD"} {
+if {${DEVICE_NAME} == "SOFA_HD"} {
  set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
 } else {
  # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
  # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
-  set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
+  set_disable_timing */*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
+  set_disable_timing */*/*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
+  #Disable cin/cout paths 
+  set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cin
+  set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cout
 }
 #
 ##########################################
@ -72,20 +87,46 @@ read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
 ##################################
 # Report timing of Connect block
 # LUT4 output timing
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in  -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
+set LUT_INPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in"
+set LUT4_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out"
+
+# Walk through all the input pin and output pin paths
+for {set ipin 0} {$ipin < 4} {incr ipin} {
+  if {0 == $ipin} {
+    report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
+  } else {
+    report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
+  }
+}
+
 # LUT3 output timing
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in  -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
+set LUT3_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out"
+
+# Walk through all the input pin and output pin paths
+for {set ipin 0} {$ipin < 3} {incr ipin} {
+  for {set opin 0} {$opin < 2} {incr opin} {
+    if {0 == $ipin && 0 == $opin} {
+      report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
+    } else {
+      report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
+    }
+  }
+}

 # Output selector timing
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+set FRAC_LOGIC_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]"
+set FF_PATH "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff"
+set FLE_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out"
+
+report_timing -from ${FF_PATH}_0/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[0] -to ${FLE_OUTPUT_PORT_NAME}[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from ${FF_PATH}_1/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
+report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[1] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt

 # LUT output to FF input timing
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
-report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+report_timing -from ${LUT4_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
+report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt

 # TODO: Carry logic timing 

--- a/SNPS_PT/SCRIPT/report_timing_io.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_io.tcl
@ -5,19 +5,23 @@
 
 ##################################
 # Define environment variables
+#
+set DEVICE_NAME "SOFA_HD"
+#set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
 set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";

-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+if {"SOFA_HD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { 
  set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
-
-#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
-#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
-
-#set DEVICE_NAME "SOFA_HD"
-set DEVICE_NAME "QLSOFA_HD"
-#set DEVICE_NAME "SOFA_CHD"
+} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+}

 set TIMING_REPORT_HOME "../TIMING_REPORTS/";

@ -26,9 +30,13 @@ set_app_var svr_enable_vpp true
 # Enable reporting ALL the timing paths even those are NOT constrained
 set_app_var timing_report_unconstrained_paths tr

+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
+  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
+} else {
  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
-
  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+}

 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"

@ -40,6 +48,9 @@ remove_lib -all
 ##################################
 # Read timing libraries
 read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
+}

 ##################################
 # Read post-PnR netlists
--- a/SNPS_PT/SCRIPT/report_timing_sb.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl
@ -5,19 +5,23 @@
 
 ##################################
 # Define environment variables
-set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
-
-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
-set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
-#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
-
-#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
-set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
-#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";

 #set DEVICE_NAME "SOFA_HD"
-set DEVICE_NAME "QLSOFA_HD"
-#set DEVICE_NAME "SOFA_CHD"
+#set DEVICE_NAME "QLSOFA_HD"
+set DEVICE_NAME "SOFA_CHD"
+
+set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
+
+if {"SOFA_HD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { 
+  set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+  set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+}

 set TIMING_REPORT_HOME "../TIMING_REPORTS/";
 # Enable preprocessing in Verilog parser
@ -25,9 +29,13 @@ set_app_var svr_enable_vpp true
 # Enable reporting ALL the timing paths even those are NOT constrained
 set_app_var timing_report_unconstrained_paths tr

+if {"SOFA_CHD" == ${DEVICE_NAME}} {
+  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
+  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
+} else {
  set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
-
  set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
+}

 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"

@ -45,6 +53,9 @@ foreach DESIGN_NAME ${DESIGN_NAMES} {
  ##################################
  # Read timing libraries
  read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+  if {"SOFA_CHD" == ${DEVICE_NAME}} {
+    read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
+  }
  
  ##################################
  # Read post-PnR netlists
--- a/SynRepoConfig/sync_files_qlsofa_hd.csv
+++ b/SynRepoConfig/sync_files_qlsofa_hd.csv
@ -1,4 +1,5 @@
 SrcLoc, DestLoc
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
--- a/SynRepoConfig/sync_files_sofa_chd.csv
+++ b/SynRepoConfig/sync_files_sofa_chd.csv
@ -1,4 +1,5 @@
 SrcLoc, DestLoc
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
--- a/SynRepoConfig/sync_files_sofa_hd.csv
+++ b/SynRepoConfig/sync_files_sofa_hd.csv
@ -2,4 +2,4 @@ SrcLoc, DestLoc
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
 FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
-SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
+HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v