From 9b3cd1f5ff02ecb3bba318eed374ebd73e1b91f0 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Wed, 6 Jan 2021 23:19:20 -0800 Subject: [PATCH] Updating task template file by calling synth_quicklogic inside yosys --- .../generate_sdc/config/task_template.conf | 5 +++-- .../generate_testbench/config/task_template.conf | 8 ++++++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf index fbf216c..cbd69be 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf @@ -28,10 +28,11 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32 arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_reg/io_reg.v [SYNTHESIS_PARAM] -bench0_top = and2 +bench0_top = io_reg +bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf index 46cfad2..987e928 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf @@ -39,7 +39,7 @@ bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v -#bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v +bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v @@ -56,16 +56,20 @@ bench22=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_tc1/rtl/*.v [SYNTHESIS_PARAM] bench0_top = and2 +bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench1_top = and2_latch +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench2_top = bin2bcd +bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench3_top = counter +bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench4_top = routing_test # RS decoder needs 1.5k LUT4, exceeding device capacity bench5_top = rs_decoder_top bench6_top = top_module bench7_top = and2_or2 bench8_top = cavlc_top -#bench9_top = cf_fft_256_8 +bench9_top = cf_fft_256_8 bench10_top = counter120bitx5 bench11_top = top bench12_top = dct_mac