mirror of https://github.com/lnis-uofu/SOFA.git
[Arch] Add openfpga arch with fracturable 18x18 multiplier
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tangxifan
parent
957d03b142
commit
990b7d4c7c
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k4_frac_cc_sky130nm.xml
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- General purpose logic block
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- K = 4, N = 8, I = 24
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- Routing architecture
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- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
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- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
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- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
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- DSP block:
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- Multi-mode multiplier which can operate in two modes
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- Mode A: 18-bit multiplier
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- Mode B: two independent 9-bit multipliers
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- Skywater 130nm PDK
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- circuit models are binded to the opensource skywater
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foundry high-density standard cell library
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="inv_01" prefix="inv_01" verilog_netlist="./inv/sky130_fd_sc_hd__inv_1.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<!-- Define a circuit model for the standard cell MUX2
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OpenFPGA requires the following truth table for the MUX2
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When the select signal sel is enabled, the first input, i.e., in0
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will be propagated to the output, i.e., out
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If your standard cell provider does not offer the exact truth table,
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you can simply swap the inputs as shown in the example below
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-->
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<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1">
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<design_technology type="cmos" topology="MUX2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in0" lib_name="A1" size="1"/>
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<port type="input" prefix="in1" lib_name="A0" size="1"/>
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<port type="input" prefix="sel" lib_name="S" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="SDFFRQ" prefix="SDFFRQ" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="DI" lib_name="SI" size="1"/>
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<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
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<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
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<port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
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<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="16"/>
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<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="DFFRQ" prefix="DFFRQ" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_prog="true" is_reset="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="EMBEDDED_IO_ISOLN" prefix="EMBEDDED_IO_ISOLN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
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<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
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<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="CARRY_MUX2" prefix="CARRY_MUX2" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v">
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<design_technology type="cmos"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" lib_name="A0" size="1"/>
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<port type="input" prefix="b" lib_name="A1" size="1"/>
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<port type="input" prefix="cin" lib_name="S" size="1"/>
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<port type="output" prefix="cout" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="mult_18x18" prefix="mult_18x18" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mult_18x18.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mult_18x18.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="A" lib_name="A" size="18"/>
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<port type="input" prefix="B" lib_name="B" size="18"/>
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<port type="output" prefix="Y" lib_name="Y" size="36"/>
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<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
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<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
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<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L1" circuit_model_name="chan_segment"/>
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<segment name="L2" circuit_model_name="chan_segment"/>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="carry_chain" circuit_model_name="direct_interc"/>
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<direct name="shift_register" circuit_model_name="direct_interc"/>
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<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" is_clock="true" default_val="0">
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<tile name="clb" port="clk" x="-1" y="-1"/>
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</global_port>
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<global_port name="Reset" is_reset="true" default_val="1">
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<tile name="clb" port="reset" x="-1" y="-1"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_ISOLN" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="CARRY_MUX2"/>
|
||||||
|
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFRQ"/>
|
||||||
|
<!-- Binding operating pb_type to physical pb_type -->
|
||||||
|
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||||
|
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1"/>
|
||||||
|
<pb_type name="clb.fle[arithmetic].soft_adder.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<pb_type name="clb.fle[arithmetic].soft_adder.carry_follower" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.carry_follower"/>
|
||||||
|
<!-- Binding operating pb_types in mode 'n2_lut3' -->
|
||||||
|
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||||
|
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:2]"/>
|
||||||
|
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
|
||||||
|
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||||
|
<port name="in" physical_mode_port="in[0:3]"/>
|
||||||
|
<port name="out" physical_mode_port="lut4_out"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||||
|
<!-- Binding operating pb_types in mode 'shift_register' -->
|
||||||
|
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block dsp -->
|
||||||
|
<pb_type name="mult_18" physical_mode_name="mult_18x18"/>
|
||||||
|
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||||
|
<pb_type name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" circuit_model_name="frac_mult_18x18" mode_bits="0"/>
|
||||||
|
<pb_type name="mult_18[mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_18[mult_18x18].mult_18x18_slice.mult_18x18" mode_bits="1" physical_pb_type_index_factor="0">
|
||||||
|
<port name="A" physical_mode_port="A[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||||
|
<port name="B" physical_mode_port="B[0:8]" physical_mode_port_rotate_offset="9"/>
|
||||||
|
<port name="Y" physical_mode_port="Y[0:17]" physical_mode_port_rotate_offset="18"/>
|
||||||
|
</pb_type> </pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
Loading…
Reference in New Issue