From 969ef7976f92b0311184295f819e1c963dbafc90 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 28 Nov 2020 15:24:54 -0700 Subject: [PATCH] [Testbench] Remove those with problems in convergence --- .../bin2bcd_post_pnr_include_netlists.v | 30 ------------------- .../counter_post_pnr_include_netlists.v | 29 ------------------ .../top_module_post_pnr_include_netlists.v | 30 ------------------- 3 files changed, 89 deletions(-) delete mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v delete mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v delete mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v deleted file mode 100644 index fd539a5..0000000 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v +++ /dev/null @@ -1,30 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:46 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "bin2bcd_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v" -`endif - diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v deleted file mode 100644 index 971d9d6..0000000 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v +++ /dev/null @@ -1,29 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:45 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "counter_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v" -`endif - diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v deleted file mode 100644 index 1790f36..0000000 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v +++ /dev/null @@ -1,30 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:49:05 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "top_module_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v" -`endif -