diff --git a/DOC/source/arch/clb_arch.rst b/DOC/source/arch/clb_arch.rst
index 0119110..415fc26 100644
--- a/DOC/source/arch/clb_arch.rst
+++ b/DOC/source/arch/clb_arch.rst
@@ -14,7 +14,7 @@ Feedback connections between LEs are implemented by the global routing architect
.. _fig_clb_arch:
-.. figure:: ./figures/clb_arch.png
+.. figure:: ./figures/clb_arch.svg
:scale: 20%
:alt: Configurable Logic Block schematic
@@ -32,7 +32,7 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
.. _fig_fle_arch:
-.. figure:: ./figures/fle_arch.png
+.. figure:: ./figures/fle_arch.svg
:scale: 30%
:alt: Logic element schematic
diff --git a/DOC/source/arch/figures/clb_arch.png b/DOC/source/arch/figures/clb_arch.png
deleted file mode 100644
index 16ac726..0000000
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diff --git a/DOC/source/arch/figures/clb_arch.svg b/DOC/source/arch/figures/clb_arch.svg
new file mode 100644
index 0000000..0795459
--- /dev/null
+++ b/DOC/source/arch/figures/clb_arch.svg
@@ -0,0 +1,662 @@
+
+
+
diff --git a/DOC/source/arch/figures/embedded_io_schematic.png b/DOC/source/arch/figures/embedded_io_schematic.png
deleted file mode 100644
index 261f452..0000000
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diff --git a/DOC/source/arch/figures/embedded_io_schematic.svg b/DOC/source/arch/figures/embedded_io_schematic.svg
new file mode 100644
index 0000000..75482cb
--- /dev/null
+++ b/DOC/source/arch/figures/embedded_io_schematic.svg
@@ -0,0 +1,253 @@
+
+
+
diff --git a/DOC/source/arch/figures/fabric_scan_chain.png b/DOC/source/arch/figures/fabric_scan_chain.png
deleted file mode 100644
index b8fdae2..0000000
Binary files a/DOC/source/arch/figures/fabric_scan_chain.png and /dev/null differ
diff --git a/DOC/source/arch/figures/fabric_scan_chain.svg b/DOC/source/arch/figures/fabric_scan_chain.svg
new file mode 100644
index 0000000..0bf9cc5
--- /dev/null
+++ b/DOC/source/arch/figures/fabric_scan_chain.svg
@@ -0,0 +1,320 @@
+
+
+
diff --git a/DOC/source/arch/figures/fle_arch.png b/DOC/source/arch/figures/fle_arch.png
deleted file mode 100644
index 3f5eb94..0000000
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diff --git a/DOC/source/arch/figures/fle_arch.svg b/DOC/source/arch/figures/fle_arch.svg
new file mode 100644
index 0000000..0384515
--- /dev/null
+++ b/DOC/source/arch/figures/fle_arch.svg
@@ -0,0 +1,293 @@
+
+
+
diff --git a/DOC/source/arch/figures/fpga_arch.png b/DOC/source/arch/figures/fpga_arch.png
deleted file mode 100644
index 696e536..0000000
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diff --git a/DOC/source/arch/figures/fpga_arch.svg b/DOC/source/arch/figures/fpga_arch.svg
new file mode 100644
index 0000000..59678b3
--- /dev/null
+++ b/DOC/source/arch/figures/fpga_arch.svg
@@ -0,0 +1,1089 @@
+
+
+
diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png
deleted file mode 100644
index 6b9b770..0000000
Binary files a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png and /dev/null differ
diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg
new file mode 100644
index 0000000..71939ce
--- /dev/null
+++ b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg
@@ -0,0 +1,247 @@
+
+
+
diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png
deleted file mode 100644
index 635f25d..0000000
Binary files a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png and /dev/null differ
diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg
new file mode 100644
index 0000000..67f148a
--- /dev/null
+++ b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg
@@ -0,0 +1,253 @@
+
+
+
diff --git a/DOC/source/arch/figures/fpga_io_switch.png b/DOC/source/arch/figures/fpga_io_switch.png
deleted file mode 100644
index b686af2..0000000
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diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/arch/figures/fpga_io_switch.svg
new file mode 100644
index 0000000..c47bc8a
--- /dev/null
+++ b/DOC/source/arch/figures/fpga_io_switch.svg
@@ -0,0 +1,408 @@
+
+
+
diff --git a/DOC/source/arch/fpga_arch.rst b/DOC/source/arch/fpga_arch.rst
index c2bf3b2..c59304e 100644
--- a/DOC/source/arch/fpga_arch.rst
+++ b/DOC/source/arch/fpga_arch.rst
@@ -14,7 +14,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS
.. _fig_fpga_arch:
-.. figure:: ./figures/fpga_arch.png
+.. figure:: ./figures/fpga_arch.svg
:scale: 25%
:alt: Tile-based FPGA architecture
@@ -72,7 +72,7 @@ When `Test_en` signal is active, users can
.. _fig_fabric_scan_chain:
-.. figure:: ./figures/fabric_scan_chain.png
+.. figure:: ./figures/fabric_scan_chain.svg
:scale: 25%
:alt: Built-in scan-chain across FPGA
diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst
index 394f588..bf73f87 100644
--- a/DOC/source/arch/io_resource.rst
+++ b/DOC/source/arch/io_resource.rst
@@ -20,9 +20,11 @@ Among the 144 I/Os,
.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
+.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`.
+
.. _fig_fpga_io_switch:
-.. figure:: ./figures/fpga_io_switch.png
+.. figure:: ./figures/fpga_io_switch.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP
@@ -43,7 +45,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f
.. _fig_fpga_io_map_wishbone_mode:
-.. figure:: ./figures/fpga_io_map_wishbone_mode.png
+.. figure:: ./figures/fpga_io_map_wishbone_mode.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
@@ -66,7 +68,7 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode
.. _fig_fpga_io_map_logic_analyzer_mode:
-.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png
+.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
@@ -98,7 +100,7 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
.. _fig_embedded_io_schematic:
-.. figure:: ./figures/embedded_io_schematic.png
+.. figure:: ./figures/embedded_io_schematic.svg
:scale: 30%
:alt: Schematic of embedded I/O cell used in FPGA