diff --git a/DOC/source/arch/clb_arch.rst b/DOC/source/arch/clb_arch.rst index 0119110..415fc26 100644 --- a/DOC/source/arch/clb_arch.rst +++ b/DOC/source/arch/clb_arch.rst @@ -14,7 +14,7 @@ Feedback connections between LEs are implemented by the global routing architect .. _fig_clb_arch: -.. figure:: ./figures/clb_arch.png +.. figure:: ./figures/clb_arch.svg :scale: 20% :alt: Configurable Logic Block schematic @@ -32,7 +32,7 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of .. _fig_fle_arch: -.. figure:: ./figures/fle_arch.png +.. figure:: ./figures/fle_arch.svg :scale: 30% :alt: Logic element schematic diff --git a/DOC/source/arch/figures/clb_arch.png b/DOC/source/arch/figures/clb_arch.png deleted file mode 100644 index 16ac726..0000000 Binary files a/DOC/source/arch/figures/clb_arch.png and /dev/null differ diff --git a/DOC/source/arch/figures/clb_arch.svg b/DOC/source/arch/figures/clb_arch.svg new file mode 100644 index 0000000..0795459 --- /dev/null +++ b/DOC/source/arch/figures/clb_arch.svg @@ -0,0 +1,662 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-17 05:15:21 +0000 + + lb + + le + + + + + + + CLB + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [7] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [0] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in5 + + + + + Cin + + + + + Cin + + + + + + + LE + [1] + + + + + out0 + + + + + out1 + + + + + in0 + + + + + in3 + + + + + reg_out + + + + + reg_in + + + + + + + + in1 + + + + + in2 + + + + + CLK + + + + + sc_in + + + + + sc_out + + + + + Test_en + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + + reg_in + + + + + sc_in + + + + + reg_out + + + + + sc_out + + + + + I0[0] + + + + + I0[1] + + + + + I0[2] + + + + + I0i[0] + + + + + CLK + + + + + Test_en + + + + + I1[0] + + + + + I1[1] + + + + + I1[2] + + + + + I1i[0] + + + + + I7[0] + + + + + I7[1] + + + + + I7[2] + + + + + I7i[0] + + + + + O[0] + + + + + O[1] + + + + + O[2] + + + + + O[3] + + + + + O[14] + + + + + O[15] + + + + + wire + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOC/source/arch/figures/embedded_io_schematic.png b/DOC/source/arch/figures/embedded_io_schematic.png deleted file mode 100644 index 261f452..0000000 Binary files a/DOC/source/arch/figures/embedded_io_schematic.png and /dev/null differ diff --git a/DOC/source/arch/figures/embedded_io_schematic.svg b/DOC/source/arch/figures/embedded_io_schematic.svg new file mode 100644 index 0000000..75482cb --- /dev/null +++ b/DOC/source/arch/figures/embedded_io_schematic.svg @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 + + switch + + boundary + + + + + + + + + + + + + CCFF_IN + + + + + + + + CCFF_OUT + + + + + + + + FPGA Fabric + + + + + SoC Interface + + + + + + + + base + + + SOC_IN + + + + + SOC_OUT + + + + + + + + + + + + + + + + + FPGA_OUT + + + + + FPGA_IN + + + + + + + + + + + + SOC_DIR + + + + + + + + + + + + + + + + + + + + + + + + + + FF + + + + + + + + + + + + PROG_CLK + + + + + + + + + + + IO_ISOL_N + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + output pin + + + + + input pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOC/source/arch/figures/fabric_scan_chain.png b/DOC/source/arch/figures/fabric_scan_chain.png deleted file mode 100644 index b8fdae2..0000000 Binary files a/DOC/source/arch/figures/fabric_scan_chain.png and /dev/null differ diff --git a/DOC/source/arch/figures/fabric_scan_chain.svg b/DOC/source/arch/figures/fabric_scan_chain.svg new file mode 100644 index 0000000..0bf9cc5 --- /dev/null +++ b/DOC/source/arch/figures/fabric_scan_chain.svg @@ -0,0 +1,320 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-17 17:11:00 +0000 + + fpga_arch + + legend + + + + + + + FPGA + + + + + + + + x + + + + + + + + y + + + + + chain + + + + + CLB + [1][12] + + + + + + + + SC_HEAD + + + + + + + CLB + [1][11] + + + + + + + + + + + + + + + + + + CLB + [1][2] + + + + + + + + + + CLB + [1][1] + + + + + + + + + + CLB + [2][12] + + + + + + + + + + CLB + [2][11] + + + + + + + + + + + + + + + + + + CLB + [2][2] + + + + + + + + + + CLB + [2][1] + + + + + + + + + + + + + CLB + [11][12] + + + + + + + + + + CLB + [11][11] + + + + + + + + + + + + + + + + + + CLB + [11][2] + + + + + + + + + + CLB + [11][1] + + + + + + + + + + CLB + [12][12] + + + + + + + + + + CLB + [12][11] + + + + + + + + + + + + + + + + + + CLB + [12][2] + + + + + + + + + + CLB + [12][1] + + + + + + + + + + + + + + + + SC_TAIL + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOC/source/arch/figures/fle_arch.png b/DOC/source/arch/figures/fle_arch.png deleted file mode 100644 index 3f5eb94..0000000 Binary files a/DOC/source/arch/figures/fle_arch.png and /dev/null differ diff --git a/DOC/source/arch/figures/fle_arch.svg b/DOC/source/arch/figures/fle_arch.svg new file mode 100644 index 0000000..0384515 --- /dev/null +++ b/DOC/source/arch/figures/fle_arch.svg @@ -0,0 +1,293 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 22:55:20 +0000 + + frac_lut4 + + 图层 1 + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + diff --git a/DOC/source/arch/figures/fpga_arch.png b/DOC/source/arch/figures/fpga_arch.png deleted file mode 100644 index 696e536..0000000 Binary files a/DOC/source/arch/figures/fpga_arch.png and /dev/null differ diff --git a/DOC/source/arch/figures/fpga_arch.svg b/DOC/source/arch/figures/fpga_arch.svg new file mode 100644 index 0000000..59678b3 --- /dev/null +++ b/DOC/source/arch/figures/fpga_arch.svg @@ -0,0 +1,1089 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-17 16:24:14 +0000 + + fpga_arch + + tiles + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + legend + + + Programmable Fabric + + + + + + + + + + + Routing Tracks + + + + + + + + + + Tile + + + + + + + I/O TileA + + + + + + + + + + + + + + I/O TileB + + + + + + + + + + + 12 + + + + + + + + + 12 + + + + + + + + tile_details + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Switch + Block + + + + + + + Configurable + Logic + Block + + + + + + + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + ... + + + + + + + X-direction + Connection + Block + + + + + + + Y-direction + Connection + Block + + + + + + + + + + + diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png deleted file mode 100644 index 6b9b770..0000000 Binary files a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.png and /dev/null differ diff --git a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg new file mode 100644 index 0000000..71939ce --- /dev/null +++ b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg @@ -0,0 +1,247 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 03:30:43 +0000 + + logic_analyzer_mode + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + + + + + + gpio[12] + + + + + gpio[20] + + + + + + + + + + gpio[136] + + + + + gpio[143] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 9 bit + + + + + Caravel + GPIO[10:2] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 3 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[125:127] + + + + + + + + gpio[21] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + + + + + + + + + + Caravel Logic Analyzer + la_data_in/out/oen[17:124] + + + + + + + + + 108 bit + + + + + + + + 4 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[13:16] + + + + + + + + + diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png deleted file mode 100644 index 635f25d..0000000 Binary files a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.png and /dev/null differ diff --git a/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg new file mode 100644 index 0000000..67f148a --- /dev/null +++ b/DOC/source/arch/figures/fpga_io_map_wishbone_mode.svg @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 03:30:43 +0000 + + wishbone_mode + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + + + + + + gpio[12] + + + + + gpio[20] + + + + + + + + + + gpio[136] + + + + + gpio[143] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 9 bit + + + + + Caravel + GPIO[10:2] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + Caravel Wishbone rst_i + Caravel Wishbone ack_o + Caravel Wishbone cyc_i + Caravel Wishbone stb_i + + + + + + + + + + + + 1 bit + + + + + + + + + + 32 bit + + + + + gpio[21] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + Caravel Wishbone we_i + Caravel Wishbone adr_i[31:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone dat_o[31:0] + Caravel Wishbone sel_i[3:0] + + + + + + + + + 69 bit + + + + + + + + + + gpio[31] + + + + + + + + + + + + 3 bit + + + + + diff --git a/DOC/source/arch/figures/fpga_io_switch.png b/DOC/source/arch/figures/fpga_io_switch.png deleted file mode 100644 index b686af2..0000000 Binary files a/DOC/source/arch/figures/fpga_io_switch.png and /dev/null differ diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/arch/figures/fpga_io_switch.svg new file mode 100644 index 0000000..c47bc8a --- /dev/null +++ b/DOC/source/arch/figures/fpga_io_switch.svg @@ -0,0 +1,408 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 03:30:21 +0000 + + switch + + base + + + + + + CCFF_TAIL -> Caravel GPIO[35] + CLK <- Caravel GPIO[36] + PROG_CLK <- Caravel GPIO[37] + + + + + + + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + + + + + + gpio[12] + + + + + gpio[20] + + + + + + + + + + gpio[136] + + + + + gpio[143] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 9 bit + + + + + Caravel + GPIO[10:2] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 3 bit + + + + + + + + 4 bit + + + + + + + + gpio[21] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + + + + + + Caravel Logic Analyzer + la_data_in/out/oen[13:127] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel + GPIO[25] + + + + + + + + + + + + Caravel Wishbone rst_i + Caravel Wishbone stb_i + Caravel Wishbone cyc_i + Caravel Wishbone we_i + + + + + + + + + Mode switch truth table: + - When Caravel GPIO[25] is logic ‘1’, FPGA is interfacing the Wishbone bus + - When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer + + + + + + + + + CCFF_HEAD <- Caravel GPIO[12] + SC_TAIL -> Caravel GPIO[11] + + + + + + SC_HEAD <- Caravel GPIO[26] + + + + + + + + + + + + + + + + + IO_ISOL_N -> Caravel GPIO[1] + TEST_EN <- Caravel GPIO[0] + + + + + 105 bit + + + + + 115 bit + + + + + + + + + Caravel Wishbone sel_i[3:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone adr_i[31:0] + Caravel Wishbone ack_o + Caravel Wishbone dat_o[31:0] + + + + + + + + + Caravel + Wishbone + clk_i + + + + + CLK + + + + + Caravel + GPIO[36] + + + + + + + + + + + + + + + + + + + + + + + Clock Switch Circuitry + + + + + diff --git a/DOC/source/arch/fpga_arch.rst b/DOC/source/arch/fpga_arch.rst index c2bf3b2..c59304e 100644 --- a/DOC/source/arch/fpga_arch.rst +++ b/DOC/source/arch/fpga_arch.rst @@ -14,7 +14,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS .. _fig_fpga_arch: -.. figure:: ./figures/fpga_arch.png +.. figure:: ./figures/fpga_arch.svg :scale: 25% :alt: Tile-based FPGA architecture @@ -72,7 +72,7 @@ When `Test_en` signal is active, users can .. _fig_fabric_scan_chain: -.. figure:: ./figures/fabric_scan_chain.png +.. figure:: ./figures/fabric_scan_chain.svg :scale: 25% :alt: Built-in scan-chain across FPGA diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst index 394f588..bf73f87 100644 --- a/DOC/source/arch/io_resource.rst +++ b/DOC/source/arch/io_resource.rst @@ -20,9 +20,11 @@ Among the 144 I/Os, .. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. +.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`. + .. _fig_fpga_io_switch: -.. figure:: ./figures/fpga_io_switch.png +.. figure:: ./figures/fpga_io_switch.svg :scale: 20% :alt: I/O arrangement of FPGA IP @@ -43,7 +45,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f .. _fig_fpga_io_map_wishbone_mode: -.. figure:: ./figures/fpga_io_map_wishbone_mode.png +.. figure:: ./figures/fpga_io_map_wishbone_mode.svg :scale: 20% :alt: I/O arrangement of FPGA IP when interfacing wishbone bus @@ -66,7 +68,7 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode .. _fig_fpga_io_map_logic_analyzer_mode: -.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png +.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg :scale: 20% :alt: I/O arrangement of FPGA IP when interfacing logic analyzer @@ -98,7 +100,7 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, .. _fig_embedded_io_schematic: -.. figure:: ./figures/embedded_io_schematic.png +.. figure:: ./figures/embedded_io_schematic.svg :scale: 30% :alt: Schematic of embedded I/O cell used in FPGA