diff --git a/DOC/source/arch/clb_arch.rst b/DOC/source/arch/clb_arch.rst index 0119110..415fc26 100644 --- a/DOC/source/arch/clb_arch.rst +++ b/DOC/source/arch/clb_arch.rst @@ -14,7 +14,7 @@ Feedback connections between LEs are implemented by the global routing architect .. _fig_clb_arch: -.. figure:: ./figures/clb_arch.png +.. figure:: ./figures/clb_arch.svg :scale: 20% :alt: Configurable Logic Block schematic @@ -32,7 +32,7 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of .. _fig_fle_arch: -.. figure:: ./figures/fle_arch.png +.. figure:: ./figures/fle_arch.svg :scale: 30% :alt: Logic element schematic diff --git a/DOC/source/arch/figures/clb_arch.png b/DOC/source/arch/figures/clb_arch.png deleted file mode 100644 index 16ac726..0000000 Binary files a/DOC/source/arch/figures/clb_arch.png and /dev/null differ diff --git a/DOC/source/arch/figures/clb_arch.svg b/DOC/source/arch/figures/clb_arch.svg new file mode 100644 index 0000000..0795459 --- /dev/null +++ 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a/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg new file mode 100644 index 0000000..71939ce --- /dev/null +++ b/DOC/source/arch/figures/fpga_io_map_logic_analyzer_mode.svg @@ -0,0 +1,247 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 03:30:43 +0000 + + logic_analyzer_mode + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[20] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 9 bit + + + + + Caravel + GPIO[10:2] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 3 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[125:127] + + + + + + + + gpio[21] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + 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a/DOC/source/arch/figures/fpga_io_switch.png and /dev/null differ diff --git a/DOC/source/arch/figures/fpga_io_switch.svg b/DOC/source/arch/figures/fpga_io_switch.svg new file mode 100644 index 0000000..c47bc8a --- /dev/null +++ b/DOC/source/arch/figures/fpga_io_switch.svg @@ -0,0 +1,408 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-19 03:30:21 +0000 + + switch + + base + + + + + + CCFF_TAIL -> Caravel GPIO[35] + CLK <- Caravel GPIO[36] + PROG_CLK <- Caravel GPIO[37] + + + + + + + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[20] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 9 bit + + + + + Caravel + GPIO[10:2] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 3 bit + + + + + + + + 4 bit + + + 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Caravel Wishbone dat_o[31:0] + + + + + + + + + Caravel + Wishbone + clk_i + + + + + CLK + + + + + Caravel + GPIO[36] + + + + + + + + + + + + + + + + + + + + + + + Clock Switch Circuitry + + + + + diff --git a/DOC/source/arch/fpga_arch.rst b/DOC/source/arch/fpga_arch.rst index c2bf3b2..c59304e 100644 --- a/DOC/source/arch/fpga_arch.rst +++ b/DOC/source/arch/fpga_arch.rst @@ -14,7 +14,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS .. _fig_fpga_arch: -.. figure:: ./figures/fpga_arch.png +.. figure:: ./figures/fpga_arch.svg :scale: 25% :alt: Tile-based FPGA architecture @@ -72,7 +72,7 @@ When `Test_en` signal is active, users can .. _fig_fabric_scan_chain: -.. figure:: ./figures/fabric_scan_chain.png +.. figure:: ./figures/fabric_scan_chain.svg :scale: 25% :alt: Built-in scan-chain across FPGA diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst index 394f588..bf73f87 100644 --- a/DOC/source/arch/io_resource.rst +++ b/DOC/source/arch/io_resource.rst @@ -20,9 +20,11 @@ Among the 144 I/Os, .. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. +.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`. + .. _fig_fpga_io_switch: -.. figure:: ./figures/fpga_io_switch.png +.. figure:: ./figures/fpga_io_switch.svg :scale: 20% :alt: I/O arrangement of FPGA IP @@ -43,7 +45,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f .. _fig_fpga_io_map_wishbone_mode: -.. figure:: ./figures/fpga_io_map_wishbone_mode.png +.. figure:: ./figures/fpga_io_map_wishbone_mode.svg :scale: 20% :alt: I/O arrangement of FPGA IP when interfacing wishbone bus @@ -66,7 +68,7 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode .. _fig_fpga_io_map_logic_analyzer_mode: -.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png +.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg :scale: 20% :alt: I/O arrangement of FPGA IP when interfacing logic analyzer @@ -98,7 +100,7 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, .. _fig_embedded_io_schematic: -.. figure:: ./figures/embedded_io_schematic.png +.. figure:: ./figures/embedded_io_schematic.svg :scale: 30% :alt: Schematic of embedded I/O cell used in FPGA