From 930f7ec4866b7c48657e7694826921d3bda7367e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 17:56:58 -0700 Subject: [PATCH] [Script] Remove task run for redundant architectures --- .../generate_fabric/config/task_template.conf | 38 ------------- .../generate_sdc/config/task_template.conf | 37 ------------- .../config/task_template.conf | 54 ------------------- .../generate_fabric/config/task_template.conf | 38 ------------- .../generate_sdc/config/task_template.conf | 37 ------------- .../config/task_template.conf | 54 ------------------- 6 files changed, 258 deletions(-) delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf deleted file mode 100644 index 9c68de0..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf deleted file mode 100644 index 32618a5..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf deleted file mode 100644 index 6fe9240..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,54 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/prepnr -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v -bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v -bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v -bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v -bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v -bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v -bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench1_top = and2_latch -bench2_top = bin2bcd -bench3_top = counter -bench4_top = routing_test -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5_top = rs_decoder_top -bench6_top = top_module -bench7_top = and2_or2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf deleted file mode 100644 index 3c1d0fc..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf deleted file mode 100644 index bd6bd45..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf deleted file mode 100644 index 69f70a1..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,54 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v -bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v -bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v -bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v -bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v -bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v -bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench1_top = and2_latch -bench2_top = bin2bcd -bench3_top = counter -bench4_top = routing_test -# RS decoder needs 1.5k LUT4, exceeding device capacity -#bench5_top = rs_decoder_top -bench6_top = top_module -bench7_top = and2_or2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test=