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Merge pull request #116 from lnis-uofu/gg_demo 

[Cleanup] Dropped old build.yml
This commit is contained in:
ganeshgore 2021-04-05 23:34:36 -06:00 committed by GitHub
parent 35628dbefb 57245e9a77
commit 91772b9155
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12 changed files with 221 additions and 247 deletions
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93
.github/workflows/build.yml vendored
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@ -1,93 +0,0 @@
name: linux_build
# Run CI on
# - each push
# - each pull request
# - scheduled weekly
on:
push:
branches-ignore:
- ganesh_dev
pull_request:
schedule:
- cron: '0 0 * * 0 ' # weekly
# Environment variables
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
MAKEFLAGS: "-j8"
# Multiple job to tests
jobs:
# Test the compilation compatibility
linux_build:
name: ${{ matrix.config.name }}
runs-on: ${{ matrix.config.os }}
# Branch on different OS and settings
strategy:
fail-fast: false
matrix:
config:
- {
name: "Quick Test: GCC-8 (Ubuntu 18.04)",
artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
os: ubuntu-18.04,
cc: "gcc-8", cxx: "g++-8",
reg_script: "quick_test.sh"
}
# Define the steps to run the build job
steps:
- name: Checkout Skywater-OpenFPGA repo
uses: actions/checkout@v2
- name: Checkout OpenFPGA repo
uses: actions/checkout@v2
with:
repository: lnis-uofu/OpenFPGA
path: OpenFPGA
submodules: true
- name: Install dependency
run: source ./.github/workflows/install_dependency.sh
- name: Checkout CMake version
run: cmake --version
- name: Checkout iVerilog version
run: |
iverilog -V
vvp -V
- name: Create CMake build environment
# Some projects don't allow in-source building, so create a separate build directory
# We'll use this as our working directory for all subsequent commands
run: cmake -E make_directory ${{runner.workspace}}/OpenFPGA/build
- name: Configure CMake
# Use a bash shell so we can use the same syntax for environment variable
# access regardless of the host operating system
shell: bash
working-directory: ${{runner.workspace}}/OpenFPGA/build
# Note the current convention is to use the -S and -B options here to specify source
# and build directories, but this is only available with CMake 3.13 and higher.
# The CMake binaries on the Github Actions machines are (as of this writing) 3.12
run: |
export CC=${{ matrix.config.cc }}
export CXX=${{ matrix.config.cxx }}
cmake $GITHUB_WORKSPACE/OpenFPGA -DCMAKE_BUILD_TYPE=$BUILD_TYPE
- name: Build
working-directory: ${{runner.workspace}}/OpenFPGA/build
shell: bash
# Execute the build. You can specify a specific target with "--target <NAME>"
run: |
cmake --build . --config $BUILD_TYPE
- name: ${{matrix.config.name}}
if: contains(matrix.config.name, 'Quick Test')
shell: bash
# Execute the test.
run: source ./.github/workflows/${{matrix.config.reg_script}}

3
.gitignore vendored
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@ -12,3 +12,6 @@
**/SDC/**/*.sdc **/SDC/**/*.sdc
!**/SDC/**/disable_configure_ports.sdc !**/SDC/**/disable_configure_ports.sdc
*/runOpenFPGA */runOpenFPGA
**/*_task/latest
**/*_task/run**
**/*_task/config/task.conf

1
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/BENCHMARK Symbolic link
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@ -0,0 +1 @@
../../BENCHMARK

48
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/efpga_12x12_sim_openfpga.xml Normal file
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@ -0,0 +1,48 @@
<!-- Simulation Setting for OpenFPGA framework
This file will use
- a fixed operating clock frequency
- a fixed programming clock frequency
Note: all the numbers are tuned to STA results from physical layouts
-->
<openfpga_simulation_setting>
<clock_setting>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher
-->
<operating frequency="50e6" num_cycles="auto" slack="0.2"/>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC
the actual programming clock frequency could be higher
-->
<programming frequency="50e6"/>
</clock_setting>
<simulator_option>
<operating_condition temperature="25"/>
<output_log verbose="false" captab="false"/>
<accuracy type="abs" value="1e-13"/>
<runtime fast_simulation="true"/>
</simulator_option>
<monte_carlo num_simulation_points="2"/>
<measurement_setting>
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measurement_setting>
<stimulus>
<clock>
<rise slew_type="abs" slew_time="20e-12" />
<fall slew_type="abs" slew_time="20e-12" />
</clock>
<input>
<rise slew_type="abs" slew_time="25e-12" />
<fall slew_type="abs" slew_time="25e-12" />
</input>
</stimulus>
</openfpga_simulation_setting>

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/openfpga_arch.xml
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@ -217,7 +217,7 @@
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>

190
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/vpr_arch.xml
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@ -1,5 +1,5 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture: SOFA HD
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
@ -11,6 +11,8 @@
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel - 100 routing tracks per channel
- Timing is loaded through an external yml file, so that we can model multiple corners
Authors: Xifan Tang Authors: Xifan Tang
--> -->
<architecture> <architecture>
@ -186,21 +188,6 @@
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -214,41 +201,32 @@
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- Give uniform delays for all the MUXes driving different length of wires
book area formula. This means the mux transistors are about 5x minimum drive strength. TODO: Can be more accurate once the report timing strategies are elaborated
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large -->
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- The wire delay is around 0.1ns in post PnR netlist.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems Create a pair of RC value so that R * C = 0.1ns
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> This is o.k. because other RC values are all zero
-->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -277,18 +255,17 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as The Embedded I/O timing is 0.11ns
the delays to and from registers in the I/O (and generally I/Os are registered FIXME: the timing may include the GPIO timing!!!
today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
@ -296,7 +273,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -306,7 +283,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -386,9 +363,9 @@
<input name="DI" num_pins="1"/> <input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -398,22 +375,22 @@
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/> <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -443,18 +420,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -462,20 +431,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
<!-- Consider the delay of the MUX between LUT3 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -505,20 +476,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
@ -526,20 +488,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -561,15 +525,27 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/> <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${REGIN_TO_FF0_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/> <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/> <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/> <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -591,52 +567,36 @@
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]"> <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]"> <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]"> <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]"> <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]"> <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]"> <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]"> <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]"> <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]"> <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]"> <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]"> <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]"> <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]"> <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]"> <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]"> <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]"> <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -650,7 +610,7 @@
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/--> <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -662,7 +622,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>

37
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_simulation.conf
View File

@ -1,4 +1,4 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments # Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
@ -8,18 +8,19 @@
[GENERAL] [GENERAL]
run_engine=openfpga_shell run_engine=openfpga_shell
power_analysis = false power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 1*60
fpga_flow=vpr_blif fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:TASK_DIR}/arch/efpga_12x12_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12 openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40 openfpga_vpr_route_chan_width=40
@ -28,12 +29,26 @@ openfpga_vpr_route_chan_width=40
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif bench0=${PATH:TASK_DIR}/BENCHMARK/and2/and2.v
bench1=${PATH:TASK_DIR}/BENCHMARK/and2_latch/and2_latch.v
bench2=${PATH:TASK_DIR}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
bench4=${PATH:TASK_DIR}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${PATH:TASK_DIR}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:TASK_DIR}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${PATH:TASK_DIR}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = top bench0_top = and2
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act bench1_top = and2_latch
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist= #end_flow_with_test=

27
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/design_variables.yml
View File

@ -1 +1,26 @@
DELAY_VALUE: 12 L1_SB_MUX_DELAY: 1.61e-9
L2_SB_MUX_DELAY: 1.61e-9
L4_SB_MUX_DELAY: 1.61e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9

14
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_fabric.openfpga
View File

@ -36,9 +36,19 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose write_fabric_verilog \
--file ./SRC \
--explicit_port_mapping \
--include_timing \
--verbose
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping write_verilog_testbench \
--file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write the SDC files for PnR backend # Write the SDC files for PnR backend
# - Turn on every options here # - Turn on every options here

45
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -1,6 +1,12 @@
# Run VPR for the 'and' design # This script is designed to generate Verilog testbenches
# with a fixed device layout
# It will only output netlists to be used by verification tools
# including
# - Verilog testbenches, used by ModelSim
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200 vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -24,11 +30,7 @@ lut_truth_table_fixup
# Build the module graph # Build the module graph
# - Enabled compression on routing architecture modules # - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules # - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs # Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation # This must be done before bitstream generator and testbench generation
@ -37,28 +39,29 @@ repack #--verbose
# Build the bitstream # Build the bitstream
# - Output the fabric-independent bitstream to a file # - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml build_architecture_bitstream --verbose --write_file arch_bitstream.xml
build_fabric_bitstream
# Build fabric-dependent bitstream # Build fabric-dependent bitstream
build_fabric_bitstream build_fabric_bitstream --verbose
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml # Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches # - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping write_verilog_testbench --file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
# Write the SDC files for PnR backend --print_top_testbench \
# - Turn on every options here --print_preconfig_top_testbench \
write_pnr_sdc --file ./SDC --print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
# Write SDC to disable timing for configure ports # Exclude signal initialization since it does not help simulator converge
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric # Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis write_analysis_sdc --file ./SDC_analysis

4
FPGA1212_SOFA_HD_PNR/Makefile
View File

@ -6,6 +6,7 @@ PYTHON_EXEC=python3.8
RERUN = 0 RERUN = 0
TB = top TB = top
OPTIONS = OPTIONS =
TASK_FILENAME ?= task_simulation.conf
.SILENT: .SILENT:
.ONESHELL: .ONESHELL:
@ -19,9 +20,10 @@ runOpenFPGA:
echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit; echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
fi fi
echo "Running ${TASK_FILENAME} task"
# =================== Clean Previous Run ================================= # =================== Clean Previous Run =================================
rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME} rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf) (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && ln -s ${TASK_FILENAME} task.conf)
# ===================== Generate Netlist ================================= # ===================== Generate Netlist =================================
(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&

2
FPGA1212_SOFA_HD_PNR/config.sh
View File

@ -2,7 +2,7 @@
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = = # = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export PROJ_NAME=FPGA1212_SOFA_HD_PNR # Project Name export PROJ_NAME=FPGA1212_SOFA_HD # Project Name
export FPGA_SIZE_X=12 # Grid X Size export FPGA_SIZE_X=12 # Grid X Size
export FPGA_SIZE_Y=12 # Grid Y Size export FPGA_SIZE_Y=12 # Grid Y Size
# Design Style [hier/flat], mostly hier # Design Style [hier/flat], mostly hier