From 295df663bbda64bfa90424db4d9cb197f691c04e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Nov 2020 15:57:05 -0700 Subject: [PATCH 1/4] [Arch] Add arch variant with soft adders --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 266 +++++++ ...n_chain_nonLR_caravel_io_skywater130nm.xml | 725 ++++++++++++++++++ 2 files changed, 991 insertions(+) create mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml create mode 100644 ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 0000000..eae5df3 --- /dev/null +++ b/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 0000000..e4602f0 --- /dev/null +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,725 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.reg_out clb.sc_out clb.cout + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 31dcd4a17f0e650897e5bf98025fda5954c8083a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Nov 2020 16:01:27 -0700 Subject: [PATCH 2/4] [HDL] Add a wrapper for HD MUX2 cell required by carry logic --- HDL/common/sky130_fd_sc_hd_wrapper.v | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 HDL/common/sky130_fd_sc_hd_wrapper.v diff --git a/HDL/common/sky130_fd_sc_hd_wrapper.v b/HDL/common/sky130_fd_sc_hd_wrapper.v new file mode 100644 index 0000000..8cadbca --- /dev/null +++ b/HDL/common/sky130_fd_sc_hd_wrapper.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:39b0368d968c2127e15ec8cc01b99e54e6d3a508ec73409b8740261b5ae15a13 +size 494 From e5a66dd47f2a58c00ed00e26f21aa4faec847139 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Nov 2020 16:14:14 -0700 Subject: [PATCH 3/4] [Script] Add task run for softadder architecture --- .../generate_fabric/config/task_template.conf | 38 +++++++++++++ .../generate_sdc/config/task_template.conf | 37 +++++++++++++ .../config/task_template.conf | 54 +++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf create mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf create mode 100644 SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf new file mode 100644 index 0000000..3c1d0fc --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=40 +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf new file mode 100644 index 0000000..bd6bd45 --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=40 +openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf new file mode 100644 index 0000000..69f70a1 --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=40 +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr +openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v +bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v +bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v +bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v +bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v +bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v +bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench1_top = and2_latch +bench2_top = bin2bcd +bench3_top = counter +bench4_top = routing_test +# RS decoder needs 1.5k LUT4, exceeding device capacity +#bench5_top = rs_decoder_top +bench6_top = top_module +bench7_top = and2_or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= From efab96d2dd7f2c5aadf47244e3c5978e437777c0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Nov 2020 16:36:31 -0700 Subject: [PATCH 4/4] [Arch] Bug fix in softadder architecture --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 100 +++++++++--------- 2 files changed, 51 insertions(+), 51 deletions(-) diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index eae5df3..1501250 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -243,7 +243,7 @@ - + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index e4602f0..847963c 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -44,7 +44,7 @@ - + @@ -124,22 +124,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -336,22 +336,22 @@ So pin equivalence should be applied to the first 3 inputs only --> - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -414,7 +414,7 @@ - + @@ -629,52 +629,52 @@ in[2]. Such twisted connection is not expected. I[0] should be connected to in[0] --> - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +