Merge pull request #42 from LNIS-Projects/xt_dev

Push-button Modelsim Verification for Specific FPGA fabric

MSIM/README.md

@@ -0,0 +1,12 @@
+# Skywater PDK
+This directory is the workspace for running Mentor Modelsim simulations for FPGA fabrics
+Please keep this directory clean and organize as follows:
+- Each task-run should be placed in a separated directory
+- **common**: include commonly used scripts for post-PnR verification 
+- READMD is the only file allowed in the directory, others should be sub-directories.
+
+* Quick Example to run simulations for task-run
+
+```
+python3 run_post_pnr_msim_task.py --testbench_dir_name ../../TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --task_name k4_N8_caravel_io_FPGA_12x12_fdhd_cc
+```

MSIM/common/modelsim_proc.tcl

@@ -9,14 +9,14 @@ proc create_project_with_close {projectname modelsim_path} {
   #Get the current project name
   set project_env [project env]
   if {$project_env eq ""} {
-      #If string empty (no project)
+    #If string empty (no project)
-      create_project $projectname $modelsim_path
+    create_project $projectname $modelsim_path
-    } else {
+  } else {
-      #If string not empty (a project is loaded so clsoe it first)
+    #If string not empty (a project is loaded so clsoe it first)
-      project close
+    project close
-      create_project $projectname $modelsim_path
+    create_project $projectname $modelsim_path
-    }
   }
+}
 
 proc add_files_project {verilog_files} {
   #Get the length of the list
@@ -30,11 +30,9 @@ proc add_files_project {verilog_files} {
 proc add_waves {top_tb} {
   add wave -position insertpoint sim:/$top_tb/*
 }
-proc runsim {simtime unit} {
+
-  run $simtime $unit
-}
 #Top procedure to create enw project
-proc top_create_new_project {projectname verilog_files modelsim_path simtime unit top_tb} {
+proc top_create_new_project {projectname verilog_files modelsim_path top_tb} {
   #Create the project
   create_project_with_close $projectname $modelsim_path
   #Add the verilog files
@@ -42,30 +40,12 @@ proc top_create_new_project {projectname verilog_files modelsim_path simtime uni
   #Compile all the files
   set myFiles [project filenames]
   foreach x $myFiles {
-    vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x
+    vlog +define+ENABLE_SIGNAL_INITIALIZATION $x
   }
   #Start the simulation
   vsim $projectname.$top_tb -voptargs=+acc
   #Add the waves
   add_waves $top_tb
   #run the simulation
-  runsim $simtime $unit
+  run -all
-  #Fit the window view
-  wave zoom full
-}
-#Top proc to recompile files and re run the simulation
-proc top_rerun_sim {simtime unit top_tb} {
-  #Save actual format
-  set myLoc [pwd]
-  write format wave -window .main_pane.wave.interior.cs.body.pw.wf $myLoc/relaunch.do
-  quit -sim
-  #Compile updated verilog files
-  set myFiles [project filenames]
-  foreach x $myFiles {
-    vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x
-  }
-  set projectname K4n4_test_fpga_msim
-  vsim $projectname.$top_tb -voptargs=+acc -do relaunch.do
-  #run the simulation
-  run $simtime $unit
 }

MSIM/common/run_post_pnr_msim_task.py

@@ -0,0 +1,76 @@
+#####################################################################
+# Python script to run ModelSim simulations for all the post-pnr testbenches
+# in a project directory
+# This script will
+# - Collect all the testbenches in a given directory
+#   For instance:
+#     ../k4_arch/pre_pnr/verilog_testbenches/and2_post_pnr_include_netlist.v
+# - Use run_post_pnr_msim_test.py to run Modelsim simulations and check results
+#####################################################################
+
+import os
+from os.path import dirname, abspath
+import shutil
+import re
+import argparse
+import logging
+import subprocess
+import glob
+
+#####################################################################
+# Initialize logger 
+#####################################################################
+logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
+
+#####################################################################
+# Parse the options
+#####################################################################
+parser = argparse.ArgumentParser(description='Run a ModelSim verification task for a tape-out FPGA')
+parser.add_argument('--testbench_dir_name', required=True,
+                    help='Specify the directory path for the Verilog testbenches')
+parser.add_argument('--task_name', required=True,
+                    help='Specify the directory path for the Verilog testbenches')
+args = parser.parse_args()
+
+#####################################################################
+# Walk through the parent directory and find all the pre-PnR testbenches
+#####################################################################
+logging.info("Finding testbenches..."); 
+
+testbench_dir_abspath = abspath(args.testbench_dir_name) + "/postpnr/verilog_testbench";
+
+testbench_files = []
+for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"):
+  testbench_files.append(globbed_file)
+
+logging.info("Found " + str(len(testbench_files)) + " testbenches")
+
+#####################################################################
+# Try to create the directory of Modelsim projects
+#####################################################################
+parent_dir_abspath = dirname(dirname(abspath(__file__)))
+msim_task_dir_abspath = abspath(parent_dir_abspath + args.task_name) + "/postpnr/verilog_testbench";
+os.makedirs(msim_task_dir_abspath, exist_ok=True)
+
+#####################################################################
+# Run ModelSim simulations for each testbench
+#####################################################################
+logging.info("Running Modelsim simulations...");
+
+num_sim_finished = 0
+
+msim_testrun_script_abspath = os.path.abspath(__file__) 
+msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
+
+for testbench_file in testbench_files:
+  # Find testbench name
+  testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
+  cmd = "python3 " + msim_testrun_script_abspath \
+      + " --verilog_testbench " +  testbench_file \
+      + " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
+      + " --testbench_name " + testbench_name + "_autocheck_top_tb"
+  subprocess.run(cmd, shell=True, check=True) 
+  num_sim_finished += 1
+
+logging.info("Done")
+logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations")

MSIM/common/run_post_pnr_msim_test.py

@@ -0,0 +1,147 @@
+#####################################################################
+# Python script to execute modelsim simulation for a given testbench netlist
+# This script will
+# - Create the tcl script to enable modelsim simulation
+# - Run modelsim simulation
+# - Analyze output log files and return succeed or failure
+#####################################################################
+
+import os
+from os.path import dirname, abspath, isfile
+import shutil
+import re
+import argparse
+import logging
+import subprocess
+
+#####################################################################
+# Initialize logger
+#####################################################################
+logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
+
+#####################################################################
+# Parse the options
+#####################################################################
+parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
+parser.add_argument('--verilog_testbench', required=True,
+                    help='Specify the file path for the Verilog testbench as input')
+parser.add_argument('--project_path', required=True,
+                    help='Specify the file path to create the ModelSim project')
+parser.add_argument('--testbench_name', required=True,
+                    help='Specify the top-level module of the testbench')
+args = parser.parse_args()
+
+#####################################################################
+# Check options:
+# - Input testbench file must be valid
+#   Otherwise, error out
+# - If the modelsim project path does not exist, create it
+#####################################################################
+if not isfile(args.verilog_testbench):
+  logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n")
+  exit(1)
+
+project_abs_path = os.path.abspath(args.project_path)
+if not os.path.isdir(project_abs_path):
+  logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
+  os.makedirs(project_abs_path, exist_ok=True)
+  logging.debug("Done\n")
+
+#####################################################################
+# Create the Tcl script for Modelsim
+#####################################################################
+# Get modelsim process tcl file path
+msim_proc_tcl_path = os.path.abspath(__file__)
+msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
+if not isfile(msim_proc_tcl_path):
+  logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
+  exit(1)
+
+# Create output file handler
+tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl"
+logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
+tcl_file = open(tcl_file_path, "w")
+
+# A string buffer to write tcl content
+tcl_lines = []
+
+tcl_lines.append("echo \"==============================\"")
+tcl_lines.append("pwd")
+tcl_lines.append("echo \"==============================\"")
+tcl_lines.append("\n")
+tcl_lines.append("set project_name " + args.testbench_name)
+tcl_lines.append("set top_tb " + args.testbench_name)
+tcl_lines.append("\n")
+tcl_lines.append("set project_path \"" + project_abs_path  + "\"")
+tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench)  + "\"")
+tcl_lines.append("\n")
+tcl_lines.append("source " + msim_proc_tcl_path)
+tcl_lines.append("\n")
+tcl_lines.append("try {")
+tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
+tcl_lines.append("} finally {")
+tcl_lines.append("\tquit")
+tcl_lines.append("}")
+
+for line in tcl_lines:
+  tcl_file.write(line + "\n")
+
+tcl_file.close()
+logging.debug("Done")
+
+#####################################################################
+# Run ModelSim simulation
+#####################################################################
+curr_dir = os.getcwd()
+# Change to the project directory
+os.chdir(project_abs_path)
+logging.debug("Changed to directory: " + project_abs_path)
+
+# Run ModelSim
+vsim_log_file_path = project_abs_path + "/vsim_run_log"
+vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
+vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
+logging.debug("Running modelsim by : " + vsim_cmd)
+subprocess.run(vsim_cmd, shell=True, check=True)
+
+# Go back to current directory
+os.chdir(curr_dir)
+
+#####################################################################
+# Parse log files and report any errors
+#####################################################################
+vsim_log_file = open(vsim_log_file_path, "r")
+
+# Error counter
+num_err = 0
+num_err_lines_found = 0
+verification_passed = False
+
+for line in vsim_log_file:
+  # Check errors from self-testing testbench output
+  if line.startswith("# Simulation finish with") :
+    num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
+    num_err_lines_found = num_err_lines_found + 1
+    if (0 < num_sim_err) : 
+      logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
+      # Add to total errors
+      num_err = num_err + num_sim_err
+  # Check total errors by Modelsim
+  if line.startswith("# Errors:") :
+    num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
+    num_err_lines_found = num_err_lines_found + 1
+    num_err = num_err + num_msim_err
+
+vsim_log_file.close()
+
+if (0 == num_err_lines_found) :    
+  logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
+elif (0 < num_err) :
+  logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
+else :
+  verification_passed = True
+
+if (verification_passed) :
+  logging.info(args.testbench_name + "...[Passed]\n")
+else :
+  logging.error(args.testbench_name + "...[Failed]\n")

TESTBENCH/common/generate_post_pnr_testbenches.py

@@ -25,49 +25,46 @@ import glob
 #####################################################################
 logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
 
+#####################################################################
+# Parse the options
+#####################################################################
+parser = argparse.ArgumentParser(description='Generate post-PnR testbenches for a given directory')
+parser.add_argument('--pre_pnr_testbench_dir_name', required=True,
+                    help='Specify the directory path for the pre-PnR Verilog testbenches')
+args = parser.parse_args()
+
 #####################################################################
 # Walk through the parent directory and find all the pre-PnR testbenches
 #####################################################################
 logging.info("Finding pre-PnR testbenches..."); 
 
-parent_dirpath = dirname(dirname(abspath(__file__)))
+pre_pnr_testbench_dir_abspath = abspath(args.pre_pnr_testbench_dir_name) + "/prepnr/verilog_testbench";
 
 # Count how many testbenches have been converted
 num_converted_testbenches = 0
 
 # Collect the pre-PnR testbenches to be converted
 pre_pnr_testbench_files = []
-post_pnr_testbench_dirs = []
+
-for root, dirs, files in os.walk(parent_dirpath):
+# Add to list 
-  for dir_name in dirs:
+for globbed_file in glob.glob(pre_pnr_testbench_dir_abspath + "/*_autocheck_top_tb.v"):
-    # Skip 'common' directory as the testbenches inside are already converted
+  pre_pnr_testbench_files.append(globbed_file)
-    # Also skip any hidden directories
+# If we have testbenches to convert, try to create the directory of post-pnr testbenches
-    if ((dir_name == "common") or (dir_name.startswith("."))):
+post_pnr_testbench_dir_abspath = abspath(args.pre_pnr_testbench_dir_name) + "/postpnr/verilog_testbench";
-      continue;
-    # Find the testbenches in the fixed location of the tree
-    curr_pre_pnr_testbench_dir_path = os.path.join(root, dir_name + "/prepnr/verilog_testbench")
-    # Add to list 
-    logging.info("Checking directory: " + str(curr_pre_pnr_testbench_dir_path))
-    for globbed_file in glob.glob(curr_pre_pnr_testbench_dir_path + "/*_autocheck_top_tb.v"):
-      pre_pnr_testbench_files.append(globbed_file)
-    # If we have testbenches to convert, try to create the directory of post-pnr testbenches
-    curr_post_pnr_testbench_dir_path = os.path.join(root, dir_name + "/postpnr/verilog_testbench")
-    post_pnr_testbench_dirs.append(curr_post_pnr_testbench_dir_path)
 
 logging.info("Found " + str(len(pre_pnr_testbench_files)) + " pre-PnR testbenches")
 
 #####################################################################
 # Try to create the directory of post-pnr testbenches
 #####################################################################
-for post_pnr_testbench_dir in post_pnr_testbench_dirs:
+os.makedirs(post_pnr_testbench_dir_abspath, exist_ok=True)
-  os.makedirs(curr_post_pnr_testbench_dir_path, exist_ok=True)
 
 #####################################################################
 # Convert pre-PnR testbenches to post-PnR testbenches
 #####################################################################
 logging.info("Converting pre-PnR testbench to post-PnR testbench...");
 for curr_pre_pnr_testbench_file in pre_pnr_testbench_files:
-  logging.info("\nProcessing " + curr_pre_pnr_testbench_file + " testbench:\n")
+  logging.info("Processing " + curr_pre_pnr_testbench_file + " testbench:")
   curr_post_pnr_testbench_file = re.sub("_autocheck_top_tb.v$", "_post_pnr_autocheck_top_tb.v", curr_pre_pnr_testbench_file)
   curr_post_pnr_testbench_file = re.sub("\/prepnr\/", "\/postpnr\/", curr_post_pnr_testbench_file)
   cmd = "python3 ./post_pnr_testbench_converter.py " \
@@ -75,6 +72,6 @@ for curr_pre_pnr_testbench_file in pre_pnr_testbench_files:
       + " --post_pnr_testbench " + curr_post_pnr_testbench_file
   subprocess.run(cmd, shell=True, check=True) 
   num_converted_testbenches += 1
+  logging.info("Done")
 
-logging.info("Done")
 logging.info("\nConverted " + str(num_converted_testbenches) + " testbenches.")

TESTBENCH/common/post_pnr_ccff_test.v

@@ -1,197 +0,0 @@
-//-------------------------------------------
-//  Verilog Testbench for Verifying
-//  Configuration Chain of a FPGA
-//	Description: This test is applicable to FPGAs which have 1 configuration
-//	chain. It will feed a pulse to the head of the configuration chain and 
-//	check if the pulse is outputted by the tail of the configuration chain
-//	in a given time period
-//
-//	Note: This test bench is tuned for the post PnR netlists
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// Design parameter for FPGA I/O sizes
-//`define FPGA_IO_SIZE 144
-//
-// Design parameter for FPGA bitstream sizes
-//`define FPGA_BITSTREAM_SIZE 65656
-
-module post_pnr_ccff_test;
-// ----- Local wires for global ports of FPGA fabric -----
-wire [0:0] prog_clk;
-wire [0:0] Test_en;
-wire [0:0] clk;
-
-// ----- Local wires for I/Os of FPGA fabric -----
-
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_IN;
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_OUT;
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_DIR;
-
-wire [0:0] prog_clock;
-reg [0:0] prog_clock_reg;
-wire [0:0] op_clock;
-reg [0:0] op_clock_reg;
-reg [0:0] prog_reset;
-reg [0:0] prog_set;
-reg [0:0] greset;
-reg [0:0] gset;
-// ---- Configuration-chain head -----
-reg [0:0] ccff_head;
-// ---- Configuration-chain tail -----
-wire [0:0] ccff_tail;
-
-// ---- Scan-chain head -----
-wire [0:0] sc_head;
-// ---- Scan-chain tail -----
-wire [0:0] sc_tail;
-
-wire [0:0] IO_ISOL_N;
-
-// ----- Counters for error checking -----
-integer num_prog_cycles = 0; 
-integer num_errors = 0; 
-integer num_checked_points = 0; 
-
-// Indicate when configuration should be finished
-reg config_done = 0; 
-
-initial
-	begin
-        config_done = 1'b0;
-	end
-
-// ----- Begin raw programming clock signal generation -----
-initial
-	begin
-		prog_clock_reg[0] = 1'b0;
-	end
-always
-	begin
-		#5	prog_clock_reg[0] = ~prog_clock_reg[0];
-	end
-
-// ----- End raw programming clock signal generation -----
-
-// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled -----
-	assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
-
-// ----- Begin raw operating clock signal generation -----
-initial
-	begin
-		op_clock_reg[0] = 1'b0;
-	end
-
-// ----- End raw operating clock signal generation -----
-// ----- Actual operating clock is triggered only when config_done is enabled -----
-	assign op_clock[0] = op_clock_reg[0];
-
-// ----- Begin programming reset signal generation -----
-initial
-	begin
-		prog_reset[0] = 1'b1;
-	#10	prog_reset[0] = 1'b0;
-	end
-
-// ----- End programming reset signal generation -----
-
-// ----- Begin programming set signal generation -----
-initial
-	begin
-		prog_set[0] = 1'b1;
-	#10	prog_set[0] = 1'b0;
-	end
-
-// ----- End programming set signal generation -----
-
-// ----- Begin operating reset signal generation -----
-// ----- Reset signal is disabled always -----
-initial
-	begin
-		greset[0] = 1'b1;
-	end
-
-// ----- End operating reset signal generation -----
-// ----- Begin operating set signal generation: always disabled -----
-initial
-	begin
-		gset[0] = 1'b0;
-	end
-
-// ----- End operating set signal generation: always disabled -----
-
-// ----- Begin connecting global ports of FPGA fabric to stimuli -----
-	assign clk[0] = op_clock[0];
-	assign prog_clk[0] = prog_clock[0];
-	assign Test_en[0] = 1'b0;
-	assign sc_head[0] = 1'b0;
-    assign IO_ISOL_N[0] = 1'b0;
-// ----- End connecting global ports of FPGA fabric to stimuli -----
-// ----- FPGA top-level module to be capsulated -----
-	fpga_core FPGA_DUT (
-		.prog_clk(prog_clk[0]),
-		.Test_en(Test_en[0]),
-		.clk(clk[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
-		.ccff_head(ccff_head[0]),
-		.ccff_tail(ccff_tail[0]),
-		.sc_head(sc_head[0]),
-		.sc_tail(sc_tail[0]),
-        .IO_ISOL_N(IO_ISOL_N)
-        );
-
-// ----- Force constant '0' to FPGA I/O as this testbench only check
-// programming phase -----
-	assign gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
-	assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
-
-// Generate a pulse after programming reset is disabled (in the 2nd clock
-// cycle). Then the head of configuration chain should be always zero
-	always @(negedge prog_clock[0]) begin
-        ccff_head = 1'b1;
-        if (0 != num_prog_cycles) begin
-            ccff_head = 1'b0;
-        end
-	end
-
-// ----- Count the number of programming cycles -------
-	always @(posedge prog_clock[0]) begin
-        num_prog_cycles = num_prog_cycles + 1; 
-        // Indicate when configuration is suppose to end
-        if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
-            config_done = 1'b1;
-        end
-
-        // Check the ccff_tail when configuration is done 
-        if (1'b1 == config_done) begin
-           // The tail should spit a pulse after configuration is done
-           // So it should be at logic '1' and then pulled down to logic '0'
-           if (0 == num_checked_points) begin
-             if (ccff_tail !== 1'b1) begin
-               $display("Error: ccff_tail = %b", sc_tail);
-               num_errors = num_errors + 1;
-             end
-           end
-           if (1 <= num_checked_points) begin
-             if (ccff_tail !== 1'b0) begin
-               $display("Error: ccff_tail = %b", sc_tail);
-               num_errors = num_errors + 1;
-             end
-           end
-           num_checked_points = num_checked_points + 1;
-        end
-
-        if (2 < num_checked_points) begin
-           $display("Simulation finish with %d errors", num_errors);
-
-           // End simulation
-           $finish;
-        end
-	end
-
-endmodule

TESTBENCH/common/post_pnr_scff_test.v

@@ -1,193 +0,0 @@
-//-------------------------------------------
-//  Verilog Testbench for Verifying
-//  Scan Chain of a FPGA
-//	Description: This test is applicable to FPGAs which have a built-in scan
-//	chain. It will feed a pulse to the head of the scan chain and 
-//	check if the pulse is outputted by the tail of the can chain
-//	in a given time period
-//
-//	Note: This test bench is tuned for the pre PnR netlists
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// Design parameter for FPGA I/O sizes
-//`define FPGA_IO_SIZE 144
-//
-// Design parameter for FPGA scan-chain sizes
-//`define FPGA_SCANCHAIN_SIZE 2304
-
-module post_pnr_scff_test;
-// ----- Local wires for global ports of FPGA fabric -----
-wire [0:0] prog_clk;
-wire [0:0] Test_en;
-wire [0:0] clk;
-
-// ----- Local wires for I/Os of FPGA fabric -----
-
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-
-reg [0:0] prog_clock_reg;
-wire [0:0] prog_clock;
-wire [0:0] op_clock;
-reg [0:0] op_clock_reg;
-reg [0:0] prog_reset;
-reg [0:0] prog_set;
-reg [0:0] greset;
-reg [0:0] gset;
-// ---- Configuration-chain head -----
-wire [0:0] ccff_head;
-// ---- Configuration-chain tail -----
-wire [0:0] ccff_tail;
-
-// ---- Scan-chain head -----
-reg [0:0] sc_head;
-// ---- Scan-chain tail -----
-wire [0:0] sc_tail;
-
-wire [0:0] IO_ISOL_N;
-
-// ----- Counters for error checking -----
-integer num_clock_cycles = 0; 
-integer num_errors = 0; 
-integer num_checked_points = 0; 
-
-// Indicate when configuration should be finished
-reg scan_done = 0; 
-
-initial
-	begin
-        scan_done = 1'b0;
-	end
-
-// ----- Begin raw programming clock signal generation -----
-initial
-	begin
-		prog_clock_reg[0] = 1'b0;
-	end
-// ----- End raw programming clock signal generation -----
-
-// ----- Begin raw operating clock signal generation -----
-initial
-	begin
-		op_clock_reg[0] = 1'b0;
-	end
-always
-	begin
-		#5	op_clock_reg[0] = ~op_clock_reg[0];
-	end
-
-// ----- End raw operating clock signal generation -----
-// ----- Actual operating clock is triggered only when scan_done is enabled -----
-	assign prog_clock[0] = prog_clock_reg[0] & ~greset;
-	assign op_clock[0] = op_clock_reg[0] & ~greset;
-
-// ----- Begin programming reset signal generation -----
-initial
-	begin
-		prog_reset[0] = 1'b0;
-	end
-
-// ----- End programming reset signal generation -----
-
-// ----- Begin programming set signal generation -----
-initial
-	begin
-		prog_set[0] = 1'b0;
-	end
-
-// ----- End programming set signal generation -----
-
-// ----- Begin operating reset signal generation -----
-// ----- Reset signal is disabled always -----
-initial
-	begin
-		greset[0] = 1'b1;
-	#10	greset[0] = 1'b0;
-	end
-
-// ----- End operating reset signal generation -----
-// ----- Begin operating set signal generation: always disabled -----
-initial
-	begin
-		gset[0] = 1'b0;
-	end
-
-// ----- End operating set signal generation: always disabled -----
-
-// ----- Begin connecting global ports of FPGA fabric to stimuli -----
-	assign clk[0] = op_clock[0];
-	assign prog_clk[0] = prog_clock[0];
-	assign Test_en[0] = ~greset;
-	assign ccff_head[0] = 1'b0;
-    assign IO_ISOL_N[0] = 1'b0;
-// ----- End connecting global ports of FPGA fabric to stimuli -----
-// ----- FPGA top-level module to be capsulated -----
-	fpga_core FPGA_DUT (
-		.prog_clk(prog_clk[0]),
-		.Test_en(Test_en[0]),
-		.clk(clk[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
-		.ccff_head(ccff_head[0]),
-		.ccff_tail(ccff_tail[0]),
-		.sc_head(sc_head[0]),
-		.sc_tail(sc_tail[0]),
-        .IO_ISOL_N(IO_ISOL_N)
-        );
-
-// ----- Force constant '0' to FPGA I/O as this testbench only check
-// programming phase -----
-	assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
-	assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
-
-// Generate a pulse after operating reset is disabled (in the 2nd clock
-// cycle). Then the head of scan chain should be always zero
-	always @(negedge op_clock[0]) begin
-        sc_head = 1'b1;
-        if (0 != num_clock_cycles) begin
-            sc_head = 1'b0;
-        end
-	end
-
-// ----- Count the number of programming cycles -------
-	always @(posedge op_clock[0]) begin
-        num_clock_cycles = num_clock_cycles + 1; 
-        // Indicate when scan chain loading is suppose to end
-        if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin
-            scan_done = 1'b1;
-        end
-
-        // Check the tail of scan-chain when configuration is done 
-        if (1'b1 == scan_done) begin
-           // The tail should spit a pulse after configuration is done
-           // So it should be at logic '1' and then pulled down to logic '0'
-           if (0 == num_checked_points) begin
-             if (sc_tail !== 1'b1) begin
-               $display("Error: sc_tail = %b", sc_tail);
-               num_errors = num_errors + 1;
-             end
-           end
-           if (1 <= num_checked_points) begin
-             if (sc_tail !== 1'b0) begin
-               $display("Error: sc_tail = %b", sc_tail);
-               num_errors = num_errors + 1;
-             end
-           end
-           num_checked_points = num_checked_points + 1;
-        end
-
-        if (2 < num_checked_points) begin
-           $display("Simulation finish with %d errors", num_errors);
-
-           // End simulation
-           $finish;
-        end
-	end
-
-endmodule

TESTBENCH/common/post_pnr_testbench_converter.py

@@ -61,6 +61,11 @@ with open(args.pre_pnr_testbench, "r") as wp:
     # Other lines can be directly copied to post-PnR Verilog testbenches
     line2output = curr_line \
     # Condition A:  
+    # Add post_pnr to top-level module name
+    if (curr_line.startswith("module")): 
+      line2output = re.sub("autocheck_top_tb;$", "post_pnr_autocheck_top_tb;", curr_line)
+    # Add sc_head and sc_tail wire definition after ccff tail definition
+    # Condition B:  
     # Add sc_head and sc_tail wire definition after ccff tail definition
     if (curr_line == "wire [0:0] ccff_tail;\n"): 
       line2output = line2output \
@@ -68,16 +73,16 @@ with open(args.pre_pnr_testbench, "r") as wp:
                   + "wire [0:0] sc_head;\n" \
                   + "// ---- Scan-chain tail ----\n" \
                   + "wire [0:0] sc_tail;\n"
-    # Condition B:  
+    # Condition C:  
     # Assign an initial value to sc_head after other ports
     elif (curr_line == "\tassign IO_ISOL_N[0] = 1'b1;\n"): 
       line2output = line2output \
                   + "\tassign sc_head[0] = 1'b0;\n"
-    # Condition C:  
+    # Condition D:  
     # Replace fpga_top with fpga_core in DUT instanciation
     elif (curr_line == "\tfpga_top FPGA_DUT (\n"): 
       line2output = "\tfpga_core FPGA_DUT (\n"
-    # Condition D:  
+    # Condition E:  
     # Add sc_head and sc_tail to the port mapping of FPGA core instance
     elif (curr_line == "\t\t.ccff_tail(ccff_tail[0]));\n"): 
       line2output = "\t\t.ccff_tail(ccff_tail[0]),\n" \

TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v

@@ -1,30 +0,0 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Fri Nov 20 15:48:46 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "bin2bcd_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v"
-`endif
-

TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v

@@ -1,29 +0,0 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Fri Nov 20 15:48:45 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "counter_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v"
-`endif
-

TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v

@@ -1,30 +0,0 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Fri Nov 20 15:49:05 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "top_module_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v"
-`endif
-